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DS90UB953-Q1: Non-Synchronous Internal Clock mode

Kiwi Fu
Prodigy 140 points
Part Number: DS90UB953-Q1

Hi Team,

In my project, 954/953 connected with coax and using POC.

Configured as non-sync internal clock mode.

954 configuration:

WriteI2C(0x4C,0x01)

WriteI2C(0x58,0x5A) 

WriteI2C(0x4C,0x01) 

WriteI2C(0x5C,0x18)  #953 ID alias

WriteI2C(0x5D,0x34)  #Sensor ID

WriteI2C(0x65,0x1A)  #Sensor ID alias

WriteI2C(0x6D,0x7C) 

WriteI2C(0x0C,0x81) 

WriteI2C(0x1F,0x02) 

WriteI2C(0x33,0x03) 

WriteI2C(0x20,0x20) 

953 configuration:

WriteI2C(0x02,0x73) 

WriteI2C(0x05,0x0B) 

WriteI2C(0x0E,0xF0) 

WriteI2C(0x0D,0x0F)

My questions:

  1. The REFCLK_VALID bit in 954  DEVICE_STS(0x04) register is 0.
    Is it correct in non-sync internal clock mode?
  2. The COAX_MODE  bit in 954 PORT_CONFIG(0x6D) register is 0.
    Should I set it to 1 in configuration?
  3. After writing configuration to 954/953, there is no error in 954 CSI_RX_STS(0x7A) register.
    But it doesn't receive any thing from sensor. Does it have any missing configuration?

Thanks!

  • 0
    TI__Mastermind 18755 points

    Hello,

    To clarify, I am assuming that you are getting LOCK/PASS since you are able to communicate to both the local and remote devices?

    1. This bit just gives the validity of the clock on the REFCLK pin. If it is not being used then it will not show a valid clock is provided.

    2. Since you are using a coax cable and power over coax then this bit will need to be set.

    3. Have you tried using the pattern generator on the 953 to see if you can get a valid signal that way?  This may help figure out where the issue is occurring.  There is an example of how to set up a basic pattern in section 7.6.4 of the 953 datasheet.  This will help verify that the deserializer is able to receive data from the serializer and may help to isolate the issue.

    Regards,

    Nick

  • 0 in reply to Nicholas Darash
    Prodigy 140 points

    Hi Nick,

    Thank you for answer.

    Yes, LOCK/PASS are both set, 954 DEVICE_STS(0x04) register = 0xCF.

    ISP side can access 954/953/sensor by I2C.

    According to 953 d/s sec.7.1.4.3,  OSCCLK_SEL select must be asserted 0x05[3]=1.

    But after trying something include pattern gen, I found if I set OSCCLK_SEL to 0 the image can be shown.

    Set OSCCLK_SEL to 1 still get nothing.

    Any hint?

    Thanks!

     

  • 0 in reply to Kiwi Fu
    TI__Mastermind 18755 points

    Hi,

    Are you able to provide the status of the link when SCCLK_SEL 0x05[3] is set to both 0 and 1.  So read register 0x04 on the 954 when this bit is set to both zero and one.  Also what are you setting CLKIN_DIV 0x05[6:4] to when you are setting SCCLK_SEL bit high?  See if it works when these bits are set to 0b000 and 0b001.

    Regards,

    Nick

  • 0 in reply to Nicholas Darash
    Prodigy 140 points

    Hi Nick,

    When 953 PLLCLK_CTRL(0x05) = 0x03, 954 DEVICE_STS(0x04) = 0xCF

    When 953 PLLCLK_CTRL(0x05) = 0x0B, 954 DEVICE_STS(0x04) = 0xC3, FPD3 can not link.

    I can sure it is not cable issue because this set of HW can work in sync-mode.

    We change it to non-sync internal clock mode because although it could work in sync-mode but the frame rate in ISP side is not stable( change between 58-62 fps).

    We would like to verify the unstable fps is not caused by 953 clock jitters.

    Please give recommend how can I debug the 953 OSCCLK_SEL can not  be set to 1 issue.

    Thanks a lot.

  • 0 in reply to Kiwi Fu
    TI__Mastermind 18755 points

    Hello again,

    Are you able to read the RX_PORT_STS registers on the 954 when OSCCLK_SEL is set to 1?  Also lets see if we can read the RX_FREQ registers on the 954 as well (0x4F and 0x50).  I want to see if there are any specific errors on the receive port and if the deserializer can recognize the forward channel frequency.

    Regards,

    Nick

  • 0 in reply to Nicholas Darash
    Prodigy 140 points

    Hi Nick,

    During checking the RX_PORT_STS & RX_FREQ, we found if delay a while after setting OSCCLK_SEL it can be set and received image is correct.

    Thanks for your help!