Part Number: SN65DSI86
Dear Sir
We want to clear follow description.
If we set 0x0A by SRC=1, DSI_CLK=460.8MHz.
But general DSI_CLK speed is dynamic decided by panel.
So how we explain 0x0A DSI_CLK=460.8Mhz but driver still could setting with 0x12 DSI_CLK value setting?
Programming guide:
When using the REFCLK as the clock source, any DSI Clock frequency is supported, but if the clock source was instead the DSI A clock, then the required DSI Clock frequency would need to change to a frequency supported by the DSI86. When operating in this mode, any one of the following DSI A clock frequencies can be used: 384 MHz, 416 MHz, 460.8 MHz, 468 MHz, or 486 MHz. In most cases, a eDP panel would support some variation from the ideal pixel clock frequency.
