• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 33 subscribers
  • Views 831 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83869HM: Is CLK_OUT capable of generating 125MHz from internal PLL?

Carlos Cabezas
Prodigy 20 points
Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869

We are willing to change our PEF7072 and AR8033 PHYs in some products to DP83869HM, but our MAC needs a constant 125MHz clock source. Other PHYs offers the possibility of generating 25 or 125MHz from the PHY xtal oscillator (direct or through PLL for 125M), but this doesn't look as a possibility in DP83869HM.

We need a confirmation for this.

  • 0
    TI__Expert 7040 points

    Hi Carlos , 

    Yes, you can use 125MHz clock from the DP83869 receive or transmit clock. Please see register 0x170h in the datasheet to select which clock to select as the CLK_OUT source. 

    Regards,

    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 20 points

    Thanks for the answer Justin, but i don't see any constant 125MHz clock option:

    0x0 = Channel A receive clock
    0x1 = Channel B receive clock
    0x2 = Channel C receive clock
    0x3 = Channel D receive clock
    0x4 = Channel A receive clock divided by 5
    0x5 = Channel B receive clock divided by 5
    0x6 = Channel C receive clock divided by 5
    0x7 = Channel D receive clock divided by 5
    0x8 = Channel A transmit clock
    0x9 = Channel B transmit clock
    0xA = Channel C transmit clock
    0xB = Channel D transmit clock
    0xC = Reference clock (synchronous to XI input clock)

    I think Ethernet channels receive or transmit clocks are not constant, as they depends on the link status, don't they?

    Regards,

    Carlos

  • 0 in reply to Carlos Cabezas
    TI__Expert 7040 points

    Hi Carlos,

    You can use register setting 0x9 = Channel B transmit clock. This 125MHz clock is derived from the PLL and not dependent on the link status. 

    Regards,

    Justin 

  • 0 in reply to Justin Lazaruk
    TI__Expert 7040 points

    Hi Carlos,

    Please program register 0x00C6 = 0010 to program the analog mux to select the clock from the PLL in order to see the 125MHz clock on CLK_OUT. 

    Regards,

    Justin