Hi,
In my custom board I am interfacing DP83822I ETH PHY to an FPGA. Since FPGA program doesnot have any softcore implemented in it, I have an MDIO core and I use it to determine link up and down status of
DP83822.
For this I try to read PHYSTS register 0x0010 Addr. My plan was to refer to PHYSTS (0) to determine Link up and down status.
but I have a different observation. I establish link and remove link manually
Here are the values I receive on reading the PHYSTS register.
After reset link down
1. Link Down (LED_0 LED OFF)
PHYSTS reads : 0x4002
2. Link up (LED_0 LED ON) Connect link
PHYSTS reads : 0x1715
3. Link Down (LED_0 LED OFF) remove link
PHYSTS reads : 0x1912
4. Link up (LED_0 LED ON) Connect link
PHYSTS reads : 0x1914
5. Link Down (LED_0 LED OFF) remove link
PHYSTS reads : 0x5912
6. Link up (LED_0 LED ON) Connect link
PHYSTS reads : 0x5F14
7. Link Down (LED_0 LED OFF) remove link
PHYSTS reads : 0x5912
8. Link up (LED_0 LED ON) Connect link
PHYSTS reads : 0x1914
9. Link Down (LED_0 LED OFF) remove link
PHYSTS reads : 0x5912
10. Link up (LED_0 LED ON) Connect link
PHYSTS reads : 0x1914
11. Link Down (LED_0 LED OFF) remove link
PHYSTS reads : 0x1912
After the initial link establishment (2) all the other occasions when i connect link, I observe LINK UP bit to be low even when LED_0 is ON. But the SPEED bit and DUPLEX bits change properly as expected.
Why is it so?? Is this correct??
How to determine Link up and down from Ethernet PHY pls advice??
I am looking for a simple mechanism .
