Hi,
As the default (Power-up), I2C is set 100ksps on TMDS181. On this mode, do customers have to meet the HW timing of STADNDARD mode or FAST Mode? Please advise us.
Thanks and best regards,
M.HATTORI
This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
Hi,
As the default (Power-up), I2C is set 100ksps on TMDS181. On this mode, do customers have to meet the HW timing of STADNDARD mode or FAST Mode? Please advise us.
Thanks and best regards,
M.HATTORI
M.HATTORI
David-san,
I have one additional question. According to I2C specification, we can find the following sentence.
The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW.
On TMDS181, does customer has to apply the above spec? Please advise us.
My customer can not operate access correctly. I seem he is satisfied with datasheet, but on his waveform, SCL high->low and SDA low->high is same timing. That is why I ask you.
Thanks and best regards,
M.HATTORI
M.HATTORI-san
The TMDS181 is fully compliant to the I 2C Bus Specification. The TMDS181 is always a slave, it is up to the master to initiate a data transfer on the bus and generates the clock signals to permit that transfer. So they need to make sure the master is i2c compliant.
Thanks
David