SMBus driven I2C device document - uncertain information?

Hey User,

I'm not an expert on the SMbus but I can atleast provide some comments on what you have.

user6317970 said:

Details:
1.) I2C has no problem with repeated start, which is in conflict with stated information "INCOMPATIBLE because of Re-START".

[Bobby] in my experience, there are some I2C slave devices which do require stop conditions in order to execute their job (like our I2C switches). The I2C spec does not talk too much in detail about starts but calls them repeated starts. (incase you want to do a quick search)

2.) The problem is in fact in the "BYTE CT" field which would not include byte count but rather DATA0. Master should count on it; Such information is missing in the figure 3.

[Bobby] I agree with you here.

3.) SMBus master would not respond to the latest data by ACK, rather by NACK.

[Bobby] I2C master would also NACK on the last byte of data it wanted to receive. An I2C slave would stop sending data after seeing the NACK. I assume an SMbus slave may not (not sure on this)

4.) If one wants to send "SUBADDRESS" to the device, previous "SLAVE ADDRESS" just have to be "W" (0). Otherwise device will send DATA0 with next clock which would be in conflict with the "SUBADDRESS" being sent by the master.

[Bobby] I'm not sure if I am following you correctly here.

For an i2C slave. If you are doing a read and already did a write using to the same slave (if it has more than one internal address), you would just send the slave address with a read bit set and data would be sent to you until you issue a stop condition. The I2C slave would already of had its internal pointer addressed, otherwise it would NACK its address.

It sounds like if you did this with an SMBUS slave, it would send you a byte count first then the first byte of data.

5.) Once "SLAVE ADDRESS" is sent like "W" (0), pure I2C device would be in write mode and would just never send anything until new Start + SUBADDRESS "R".

[Bobby] This is correct. For an I2C write, the master is sending data and the slave will only take control of the SDA line to ACK. An I2C read must include a separate transaction where the master sends the slave address followed by the read bite set, immediately afterwards the ACK and following byte are generated by the slave.

I hope this helps. The last image in figure 3 seems incorrect to me, It looks like the R/W should be set to '1' (read) instead of 0(write) unless the SMBus has a command to issue a read while the write bit is set to 0.....

-Bobby

Hi Bobby,

Thank you very much for answer. Will TI provide some errata to this document (sloa132.pdf)?

If yes then I'd like to have a link. That's all from my side.

Have a nice day,

Jiří