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DP83867CR: Two devices with DP83867CR Ethernet PHYs can not establish 1 Gbps link when connected together

user4998718
Prodigy 165 points
Part Number: DP83867CR

Hi!

I have a problem when connecting two boards equipped in DP83867CR Ethernet PHYs. These boards are based on Zynq Ultrascale+ MPSoC. They can establish 1 Gbps link with different devices as PC or switch, but can not do it for two the same boards. When a cable is inserted into ports there is not any Linux reaction. Link is not detected. When I reduce speed on one board to 100 Mbps then link is detected, but one board reports:

macb  ff0e0000.ethernet eth1: unable to generate target frequency: 25000000 Hz
macb  ff0e0000.ethernet eth1: link up (100/Full)

but second:
macb  ff0e0000.ethernet eth1: unable to generate target frequency: 125000000 Hz
macb  ff0e0000.ethernet eth1: link up (1000/Full)

Auto-negotiation is active (checked with ethtool). I don't understand this mismatch. When I reduce the link speed for both then they work properly. Why they can work with different devices, but can not together at 1 Gbps link? Do you have any idea? What could be a reason?

Hardware: Zynq US+ with DP83867CR
Kernel: Linux 4.19 from Xilinx

Thanks for any reply!

Paweł

  • 0
    TI__Genius 9920 points

    Hi Paweł

    What is the set up for your two PHYs? When you say auto-negotiation is active, are they both set in Auto-Negotiation or forced mode? Likewise, are your link partners also set up in a similar way? 

    When you have it set to 1GB speed, can you confirm that you see a 125MHz on the RX CLK and TX CLK?

    Thanks

    Cecilia

  • 0 in reply to Cecilia Reyes
    Prodigy 165 points

    Hi Cecilia!

    Which details about setup do you need? Both work in an auto-negotiation mode, but forcing to 1 Gbps does not make a situation better. The link partner is configured the same way. I made some tests with using iperf3 tool and the transfer was much higher than 100 Mbps (it was ~940 Mbps for both directions with PC as an iperf3 server). It seems me that  the result is impossible to achieve without correct clock speed. Do you think clocks are imperfect?

    Thanks
    Paweł

  • 0 in reply to user4998718
    TI__Genius 9920 points

    Hi Paweł

    Can you please share your schematic for the two PHYs? 

    This could be a timing issue between your TX CLK and RX CLK. Could you please try configuring between the different modes outlined in the datasheet in section 8.4.1.1.2-1000Mb Mode Timing?

    Thanks,

    Cecilia

  • 0 in reply to Cecilia Reyes
    Prodigy 165 points

    I solved the problem. There was an auto-negotiation enabled for speed, but not for master/slave resolution.

    Cecilia, thank you for replies.

    Paweł