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DS90UB933-Q1: GPIO Delay through serializer

Steve Widener
Genius 11010 points
Part Number: DS90UB933-Q1

Do we have any information on how long it takes to go from; a digital change on parallel input serialized, passed over the FPD-LINK III, deserialized and then appear at the parallel output of a companion DS90UB934?

Also, can you clarify the spectrum that is used to transmit both the serialized channel and the bidirectional data channel? I can see a lot of talk about spread spectrum and that the bandwidth is max 100 MHz, but nothing about the centre frequencies.

  • 0
    TI__Mastermind 18755 points

    Hello,

    Are you asking about the forward channel latency? Specifically the delay between serializing the data and sending it over then deserializing? So latency is typically calculated as a function of the forward channel assuming worst-case scenario 2xFC frame.  So the forward channel is 28 symbols so we can do 2*symbols*FC_Frequency (2*28*1ns) = 56ns.  This assumes 1GHz FC frequency.

    And for the spread spectrum frequency the center frequency depends on the pixel clock frequency.  And the 100MHz is the maximum pixel clock frequency it will work with.  Refer to figure 9 on the 934 datasheet.

    Regards,

    Nick

  • 0 in reply to Nicholas Darash
    TI__Genius 11010 points

    Follow-up questions ->

    1.       For the spread spectrum centre frequency, where it “depends” on the pixel clock, does this mean this is a 1 to 1 dependence? By this I mean, if I supply a 50 MHZ Pixel clock, will the centre frequency of the RF signal sent over FPDLINK III be 50 MHZ?

    2.       What’s the bandwidth of the spread spectrum signal around this centre frequency? In Figure 9 of the 934 datasheet, this looks like fdev. But fdev is listed as a characteristic of the output LVCMOS I/O, not of the FPD LINK III, so I’m not currently interpreting as an RF bandwidth.

  • 0 in reply to Steve Widener
    TI__Mastermind 18755 points

    Hi again,

    So yes the center frequency would be the pixel clock frequency.  I was mistaken, the pixel clock is not capped by this feature its not capped at 100MHz. The clock signal is frequency modulated by a triangle wave with a frequency of Fpclk/3168 + or - 1%.  So fdev is + or - 1% of the pixel clock frequency (Fpclk) and fmod is Fpclk/3168.

    In other words Fpclk will deviate between Fpclk+ and Fplck- which are +1% and -1% of Fpclk respectfully.  The frequency at which the clock frequency will vary between the two frequencies is Fpclk/3168 which is selected in register 0x3E.

    Regards,

    Nick