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TCA9548A: Cio(ON)

K.Yaita
Guru 29720 points
Part Number: TCA9548A


Hi Team,

TCA9548A datasheet shows the following about Cio(ON).



Do you have internal capacitance value? I assume external capacitance is zero in this case.
I believe internal capacitance value is considerably smaller than Cio(OFF). Is my understanding correct?

Best Regards,
Yaita

  • 0
    TI__Guru 62920 points

    Hello Yaita-san,

    What that note means is that the CIO(off) is the capacitance of the device itself. When the switch is enabled, though, you would need to add to this any additional external capacitance on the other side of the switch when considering total capacitive loading.

    Regards,

    Max

  • 0 in reply to Miguel Robertson
    Guru 29720 points

    Hi Max-san,

    Do you refer the following is correct?
    Cio(ON) = Cio(OFF) + external capacitance on the other side of the switch

    I have thought Cio(OFF) is almost source-drain capacitance of internal switches and the capacitance is negligible when switch is enabled.

    Best Regards,
    Yaita

  • 0 in reply to K.Yaita
    TI__Guru* 75871 points

    Hey Yaita-san,

    Cio(ON) = Cio(off) of enabled channels (this includes the internal parasitic caps of the main SDA/SCL and enabled secondary SDA/SCL) + external parasitic capacitance on enabled channels

    Example if you have ch0 and ch2 enabled. Your total capacitance would be:

    28pF(max main) + 7.5pF (max from ch0) + 7.5pF (max from ch2) + any parasitic capacitance on main/ch0/ch2

    You are correct when you say the source to drain capacitance from the pass FET is negligible. If we treat the pass FET as a short/low impedance when channels are enabled then we will see the intrinsic capacitance at the pins to be in parallel (meaning they add together). However the leadframe of the package and bond wires add additional parasitic which are included in the spec which can be as large as 5pF.

    The main channel has higher capacitance than the other channels due to the input stage and output stage of the state machine plus all the pass FET parasitics tied to the main channel. (SCL is actually slightly lower because it does not have a a pull down FET like the SDA pin does to ACK when it is addressed).

    I2C spec allows for the main channels to be larger than 10pF of capacitance as an exception to the 10pF limit for I2C slaves so this is not a problem.

    Thanks,

    -Bobby