SN65DSI86: 4K 30fps 24bpp Support

Hi David,

My customer used SoC is Qualcomm 810.

The spec mentions that it’s (4096 × 2160 with FBC (two MIPI combined)).

Can this IC(SN65DSI86) support FBC method?

Thank you.

Regards,

Jim

Upload the spec.

Jim

The DSI86 expects the GPU to provide video timing events and active pixel data in the proper order in the form of a real-time pixel stream. Please refer to section 8.4.4.5 and make sure Qualcomm follows the DSI specification [DSI]. The timing events can be provided in one of two types: Sync Pulses, and Sync Events. The vsupports both types. For the Sync Pulse type of timing event, the GPU will send VSYNC START (VSS), VSYNC END (VSE), HSYNC START (HSS), and HSYNC END (HSE) packets. For Sync Event type, the GPU will only send the sync start packets (VSS and HSS). For both types of timing events, the DSIx6 will use the values programmed into the Video Registers to determine the sync end events (VSE and HSE). Please note when configured for dual DSI channels, the SN65DSI86 will use VSS, VSE, and HSS packets from channel A. The DSIx6 will use channel A events to recreate the same timings on the DisplayPort interface. The VSS, VSE, and HSS packets from channel B are used to internally align data on channel B to channel A.

Thanks

David

Hi David,

Could you help to confirm if SN65DSI86 support 3840x2160@60Hz,8 bits color(24bpp)? They still require to use all 8 DSI lanes, am I right?

Thank you.

Regards,

Jim