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DS90UB934-Q1: vsync output is delayed compared to hsync/pxclk

Sabrina Chang1
Prodigy 50 points
Part Number: DS90UB934-Q1
Other Parts Discussed in Thread: DS90UB913A-Q1, , DS90UB954-Q1

Hi,

I'm bringing up DS90UB934-Q1 with DS90UB913A-Q1

The DS90UB913A-Q1 has been verified with DS90UB954-Q1 and it is working fine.

But the output timing of VSYNC from 934 is delayed compared to HSYNC and PXCLK.

Below is the waveform I've measured. Yellow: VSYNC, Blue: HSYNC

Is there any FV polarity that I should set on DS90UB934-Q1? Or any other suggestion?

When 913 works with 954 , I do set reg0x7c=0x1 on 954 for frame valid is low and line valid is high.

Thanks.

  • 0
    TI__Expert 3390 points

    Hi Sabrina,

    Edit: The method you are using to trigger on the scope is not correct. If your scope has an option, the method you use is A-B trigger and you have to trigger after "n" events where n is the number of lines. This way you'll actually be able to view Vsync and Hsync together in a scope. Right now you are just triggering on Vsync and Hsync is just floating.

    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

    In addition to the above, I had some further comments to help you if the above recommendation doesn't fix the issue. Just to confirm, this is the HSYNC and VSYNC at the output? If so, can you do a capture of the VSYNC and HSYNC at the input to the serializer, so the camera output. Then we can compare the two captures. What do you mean by frame valid polarity? Like if the signal should have a falling edge when viewing it in a scope? then yes, you should be seeing a falling edge as shown below. You're making sure that the probe is connected correctly right? On the 954, if you set 0x7c = 0x00, does it have issues then?

    Regards,
    Mandeep Singh

  • 0 in reply to Mandeep S
    Prodigy 50 points

    Hi Mandeep,

    My scope cannot set trigger source from 2 channel. Even though I just trigger on Vsync, the time domains of the 2 signal are the same.

    The thing is my VSYNC is valid when it is low, and blanking when it is high. It's inverted compared to your graph. 

    My HSYNC is valid when it is high, and blanking when it is low. It's the same as your graph.

    I'm very sure the probe is connected right. My backend ISP cannot receive correct number of lines and I guess it's because of the incorrect timing of VSYNC.

    With 0x7c=0, 954 cannot work properly.

    Best,

    Sabrina

  • 0 in reply to Sabrina Chang1
    TI__Expert 3390 points

    Hi Sabrina,

    Can you capture the VSync at the input of the serializer? I'm wondering if this is being generated by the imager of the SerDes is actually causing it to invert.

    Regards,
    Mandeep Singh

  • 0 in reply to Mandeep S
    Prodigy 50 points

    Hi Mandeep,

    Since the design board of serializer comes from 3rd party, I'm still asking for the schematics. Will back to you if I get the data.

    I'm wondering can 934 work when line valid and frame valid polarity are different?

    Will 934 do some processing when the VSYNC/HSYNC are decoded from FPD-link?

    Thanks!!

    Best,

    Sabirna

  • 0 in reply to Sabrina Chang1
    TI__Expert 3390 points

    Hi Sabrina,

    The 933->934 is a parallel-in/parallel-out interface, so it will pass the signals through regardless of polarity. Therefore, it should work regardless of polarity as there are some sensors that do actually transmit video lines during a low VSYNC period.

    Regards,

    Mandeep Singh