• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 33 subscribers
  • Views 759 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB954-Q1: What are data bit rate and DDR clock frequency?

Yoshiki Ochi
Genius 9455 points
Part Number: DS90UB954-Q1
Other Parts Discussed in Thread: DS90UB935-Q1, DS90UB953-Q1

Hi team, 

What are data bit rate HSTXDBR and DDR clock frequency fCLK shown in "6.7 AC Electrical Characteristics CSI-2"? Could you tell me how to use these parameters? 

Does HSTXDBR mean the output CSI-2 data bit rate per line? If so, should we use data bit rate per lane with 416~1664 Mbps while RCLK=26MHz?

Is fCLK same as fCLKIN in datasheet? I want to confirm RX and TX data bit rate per line is suitable or not. Could you tell me my understanding in below examination is correct or not?

↓"7.4.1 CSI-2 Mode" in datasheet

In CSI-2 mode each deserializer Rx Port can support an FPD-Link line rate up to 4.16 Gbps (RX data rate pen line should be below 4.16Gps, is it correct?), where the forward channel and back channel rates are based on the reference frequency used for the serializer:

In Synchronous mode based on REFCLK input frequency reference, the FPD-Link line rate is a fixed value of 160 × REFCLK. FPD3_PCLK = 4 × REFCLK and Back channel rate = 2 × REFCLK. For example with REFCLK = 25 MHz, line rate = 4.0 Gbps, FPD3_PCLK = 100 MHz, back channel data rate = 50 Mbps. The sensor CSI-2 rate is independent of the line rate and Tx CSI-2 rate in synchronous clocking mode and can be up to 3.328 Gbps  (Does it indicate per line data bit? If so, we should use each TX line under 3.328 Gbps data rate?)

In Non-synchronous clocking mode when the DS90UB953-Q1 or DS90UB935-Q1 uses external reference clock (fCLKIN) the FPD-Link line rate is typically fCLKIN × 80, FPD3_PCLK = 2 × fCLKIN or 1 x fCLKIN and back channel data rate is set to 10 Mbps. For example, with fCLKIN = 50 MHz, line rate = 4Gbps, FPD3_PCLK = 100 MHz, and the back channel rate is 10 Mbps. The sensor CSI-2 rate is independent of the fCLKIN.

In CSI-2 non-synchronous clocking mode the DS90UB953-Q1 uses the CSI-2 clock for a reference. The (CSI_CLK) the FPD-Link line rate is typically CSI_CLK × 10, FPD3_PCLK = 1/4 × CSI_CLK and back channel rate is set to 10 Mbps. For example with CSI_CLK = 400 MHz, line rate = 4.0 Gbps, FPD3_PCLK = 100 MHz, the back channel data rate is 10 Mbps. When using the non-synchronous CSI-2 clocking mode, the user must be certain the CSI-2 source meets the stringent jitter requirements for the serializer reference and the CLK lane is always active.

Regards,
Ochi

  • 0
    TI__Genius 11340 points

    Hi Ochi-san,

    The HSTXDBR CSI-2 data rate it's the actual number of bits per second per lane. The DDR clock frequency is the same as the data rate but represented in MHz (so divided by 2).

    Do you mean fCLKIN as the clock input to the serializer? CLKIN is only used in non-sync mode, for sync mode, you don't need a CLKIN, and the DDR clock is what's being outputted on the clock lanes of the CSI transmitters. The DDR clock is derived from the REFCLK from the deserializer. In synchronous mode, the forward channel rate is derived from the back channel, which is also derived by REFCLK.

    From section 7.4:

    You are correct that in sync mode, the RX line rate can be up to 4.16Gbps, and CSI bandwidth can be up to 1664Mbps/lane. The 3.328Gbps is a typo.

    Best,

    Jiashow

  • 0 in reply to Jiashow Ho
    TI__Genius 9455 points

    Hi Jiashow, 

    Thank you very much!

    Regards,
    Ochi