DP83849I: PHY output pins ESD protection

Hi Vitaliy,

ESD structures are TI proprietory. Kindly do share the concern with ESD and we can clarify if on-chip ESD will suit the requirement or not.

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Regards,

Vikram 

Hi Vikram,

Thank you for your reply. In our application we are required to survive a lightning transients into the output of the Ethernet transformer.  The standard test is to inject the lighting pulse directly into one of the pins (Tx- and TX+  or RX- or RX+ are not tied together).  Even though there's galvanic isolation, there's still concern that fast DV/DT pulse will couple to the primary side and reach the PHY even though highly attenuated. 

Before considering putting protection on the primary side (see attached) and doing much more detail analysis of the parasitics in the transformer,  I'd like to understand what kind of protection does the PHY itself has against OV transients like ESD.  Our early tests with external protection, high speed, low capacitance TVS array distorted the waveform out of compliance with IEEE spec.  So we are looking for other options.

Hi Vitaliy,

By any chance do you have the snapshot of the expected waveforms on ETHA_TX+/TX-/RX+/RX- pins. What I am looking for is the expected magnitude of the pulse on these pins and duration of that pulse.

We dont have a direct data on how big and how long the voltage transient we can support on these pins. But I can try to map it with ESD like event and see if the transients can still be safe for the device? 

Also what is the expectation about the data transfer during lightning event? Is link-drop and auto-recovery ok? Can you tell me a little bit more about the application so that we can find the correct work-around for you if required?

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Regards,

Vikram

I can describe approximately:

Differential transient voltage at the pins of the PHI (TX+, Tx- and RX+, RX- as listed in previous reply) into 100 ohm load (with PHY removed) can reach  ~234V  for about 200 nanoseconds.

with peak current ~3-4 amps for 200ns.  

Common mode voltage froe pins of the PHI (TX+, Tx- and RX+, RX- as listed in previous reply) to the common ground:  140V, 2.5A peak for ~150ns

For energy calculation, wave shape can be assumed square pulse.

Numbers above are extrapolated from actual lighting event levels, there's some uncertainty.

We are allowed to have data drop during lighting event as long as recovery happen.

Thank you for looking into that.  Any information on clamping would be helpful.

Hi Vikram,

Have you had a chance to look into these?  The biggest question I'd like to know if there're any sort of ESD clamping diodes and what ESD levels then can handle.  

We'll do the analysis how those compare to what we are planning to see.  

Thank you .

Hi Vitaliy,

I was trying to see how close it is to the ESD kind of event which our ESD structures can take care without damaging the phy. But these mentioned voltage/current peaks and durations are much higher.

Here are the ESD like events that we have tested and I see that duration of current is much higher in your test.

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Regards,

Vikram