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TMDS181: Trigger of DDC clock stretch

Kazuki Kuramochi
Genius 11065 points
Part Number: TMDS181


Hello Expert,

I have question for TMDS181's DDC clock stretch in receiver side application.

Datasheet recommended to use TMDS181 as snoop mode for receiver application because several equipment don't support clock stretch.

Then I'd like to know about the clock stretch's operation trigger.
I think it will happen when SCL keep Low when communicating to Source side. However we'd like to know about the detailed timing information.(e.g. how long does low is needed for happening clock stretch)

Would you provide it?


I'm looking forward to hearing back from you.

Best regards,
Kazuki Kuramochi

  • 0
    TI__Guru**** 181921 points

    Kuramochi-san

    Please refer to Table 10, Note 4 of the I2C spec for the clock stretching timing requirement: https://www.nxp.com/docs/en/user-guide/UM10204.pdf.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    TI__Genius 11065 points

    Hello David-san,

    Sorry for my late reply.
    I understand about what is trigger of causing clock.

    Sorry, I have one more thing to ask.
    TMDS181's datasheet recommend to use snoop mode under receiver side application.
    I think there isn't risk of communication error on DDC line regarding clock stretch in spite of master/slave control mode if receiver side device don't support clock stretch.
    Is this understanding correct? Or is there any risk which is in TMDS181 DDC circuitry?

    Best regards,
    Kazuki Kuramochi

  • 0 in reply to Kazuki Kuramochi
    TI__Guru**** 181921 points

    Kuramochi-san

    There is no issue if the slave does not support clock stretching. Clock stretching is optional.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    TI__Genius 11065 points

    David-san,

    This is just confirmation but I'd like to know the function of DDC block.
    Are DDC block's function isolation and buffer? Or is there the other function?

    Best regards,
    Kazuki Kuramochi

  • 0 in reply to Kazuki Kuramochi
    TI__Guru**** 181921 points

    Kuramochi-san

    The TMDS181 acts as a I2C repeater, not just a level shifter - an I2C slave on the source facing side and an I2C master on the sink facing side. As an I2C slave, the TMDS181 implements clock stretching. So the TMDS181 can hold SCL low on the source side while waiting for a response from the SNK. 

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    TI__Genius 11065 points

    David-san,

    Sorry but I little confused.
    I thought there is not some kind of risk of causing unexpected clock stretch if source side and sink side don't support clock stretch.
    But you explained that TMDS181 will cause clock stretching by itself.
    So does it mean there is possibility of occurring communication error from unexpected clock stretching by TMDS181 in spite of source side and sink side don't support clock stretch?

    Best regards,
    Kazuki Kuramochi

  • 0 in reply to Kazuki Kuramochi
    TI__Guru**** 181921 points

    Kuramochi-san

    For source/sink that do not support clock stretching, we recommend using the TMDS181 DDC snoop mode. 

    The TMDS181 utilizes clock stretching for DDC transactions. As there are sources and sinks that do not perform this function correctly a system may not work correctly as DDC transactions are incorrectly transmitted/received. To overcome this a snoop configuration can be implemented where the SDA/SCL from the source is connected directly to the SDA/SCL sink. The TMDS181 will need its SDA_SNK and SCL_SNK pins connected to this link in order to correctly configure the TMDS_CLOCK_RATIO_STATUS bit. Care must be taken when this configuration is being implemented as the voltage levels for DDC between the source and sink may be different, 3.3 V vs 5 V

    For source/sink that do support clock stretching, you can connect TMDS181 DDC_SNK to the sink and DDC_SRC to the source.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    TI__Genius 11065 points

    David-san,

    I understand that TMDS181's DDC block utilize DDC transaction for implementing clock stretch so there is risk of unexpected Clock stretch from suddenly end of communication or anything in spite of Sink and Source side don't support clock stretch.

    Best regads,
    Kazuki Kuramcohi