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SN65HVD72: SN65HVD75 Failsafe behavior

Jason Kelly3
Prodigy 10 points

Part Number: SN65HVD72

Hello,

We use the SN65HVD72 on our product (slave device). A customer is using our product in their system and is sending collisions to our device. After they send a collision our device becomes unresponsive to them on the bus. We assume those collisions are essentially causing a short. We're unsure of which of the two below is most probable:

  1. The short causes a current surge
    1. The current surge is causing the LDO in front of it to drop out. LDO has a maximum current of 150 mA
    2. LDO drops out and it causes issue with our processor from coming back up properly

  2. The SN65HVD72 is entering failsafe mode due to shorting and becomes unresponsive because failsafe mode persists.

And then my main question is, when the chip enters failsafe, does failsafe persist until the chip is shut down? Or is the failsafe behavior only during the short circuit. If the chip remains in failsafe mode then I would be able to understand why the bus becomes unresponsive after sending a collision.

  • 0
    TI__Guru 62920 points

    Hi Jason,

    There's not really a failsafe mode per se.  What failsafe means for this device is that if there is a condition that results in a differential input voltage of 0 V, the receiver output logic state will be high (the same as if it received some positive differential input, i.e., VA > VB).  This could occur if A is shorted to B, if the device is disconnected from a bus, or if the bus is idle in a high-Z state with no external biasing.  So, there is no recovery time associated with leaving this state - any low-level differential inputs beyond the "VIT-" specification should make the receiver output low regardless of the previous output state (assuming /RE is low as well).

    When a collision occurs, the SN65HVD72 will contend with the collision when they drive opposite states, resulting in higher currents from the driver outputs.  The worst-case output current is limited by the "IOS" specification of the transceiver, which in this case is 160 mA.  So, it sounds like there is some risk here that the LDO is losing regulation.

    Let me know if this isn't clear or if I could give any further help.

    Regards,
    Max