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TS2PCIE2212: query for this application : PCIe shared access for slave IC

Part Number: TS2PCIE2212
Other Parts Discussed in Thread: HD3SS3212

// for TSPCIE2212 IC, I don't read the spec deeplu, I just selected for writing this question. 

Hi TI,

I have a question for below figure.

is there any PCIe switch (or hub) to access Slave ICs for each SoCs ? 

Thanks

  • The HD3SS3212 can perform this type of function as a passive mux or switch between the devices.  Using a passive mux like the HD3SS3212 in this type of application would have to be integrated into the system hardware and software design.  This is most common in client systems.  In a larger server style system this application is usually supported by an active switch (not made by TI).

    Regards,

    Lee

  • Hi Lee, 

    Very thanks for your answer, I will check this IC, HD3SS3212

  • Hi Lee, 

    there is one more question,

    in this datasheet, there are figures 4,5,6.

    they show the configuration controller and device/endpoint.

    I wonder :

    q) For B and C port configuration w/ PCIe, does it use only PCIe endpoint ? 

     can I use tow PCIe RC controller in each B and C port ? 

  • // additional description 

    I wonder, how can I configure the Rx, Tx and clock lane for PCIe..

    I think this IC has only Rx and Tx port (no clock) when I wanna use PCIe i/f. 

    =====================================

    Hi Lee, 

    there is one more question,

    in this datasheet, there are figures 4,5,6.

    they show the configuration controller and device/endpoint.

    I wonder :

    q) For B and C port configuration w/ PCIe, does it use only PCIe endpoint ? 

     can I use tow PCIe RC controller in each B and C port ? 

  • Hi,

    These devices are passive and bi-directional, so it is okay to use endpoints or root complexes to drive and receive signals through the device.  The application is typically one which uses multiple endpoints as shown in the graphics.

    The PCIe clock is not routed through the passive switches.  The PCIe endpoint and root complex will all typically receive individual copies of the 100 MHz PCIe Reference Clock signal.

    Regards,

    Lee