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DP83848I: Ethernet link no more working at 100M; but only 10M with LPC23xx

olivier descoubes
Prodigy 40 points
Part Number: DP83848I

Hello,

I am using the LPC2366 with the DP83848 since several years, working fine until now : with the change of processor manufacturing date code (previous date code was year 2007, and now date code is year 2018) : with this latest date code, the ethernet link works only at 10M , and no more at 100M.

Has anybody already been faced with this problem?

Olivier

  • 0
    TI__Expert 7040 points

    Hi Olivier, 

    Are you establishing link through Auto-Negotiation or forced mode? Please provide strap configuration of the auto-negotiation pins and register data. Registers 0x00h, 0x04h, and 0x10h provide information about the auto-neg process.

    Are you seeing this issue across multiple DP83848I PHYs, and does the same PHY recover 100M link when an old date code processor replaces the new processor?

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 40 points

    Dear Justin,

    Normally, we work with auto-negotiation; Here we have to force to 10M to make it work; if we force to 100M, it doesn't work (and with the 'old' processor, it works).

    register 0x00 : PHY_FULLD_100M      0x2100      /* Full Duplex 100Mbit               */

    register 0x04 unchanged by our firmware

    register 0x10 : 0x0004 and then 0x0005 (@100MBit)  0x0006 and then 0x0007 (@10MBit)

    Also, when set to 100Mb, the Eth link connect/disconnect is detected, and the RJ45 LEDs are blinking.


    while replacing the year 2018 date code processor by a year 2007 processor, on the same board, the 100M works; We try several boards, always the same result (we have produced 400 boards...)
    do you have any test board using a 20MHz oscillator for the LPC23xx ?

    We use a 20MHz oscillator for the LPC2366, and a 50MHz oscillator for the DP83848. Both signals are clean;

    Do you have any suggestion for testing hadrware/registers... ?  This issue is absolutely critical for us !

    Best regards
    Olivier

  • 0 in reply to olivier descoubes
    TI__Expert 7040 points

    Hi Olivier, 

    Thank you for the clarification.

    1. Can you please provide the register value read in register 0x04? This will help identify what strap settings are being latched in. 
    2. When you say register 0x10 : 0x0004 and then 0x0005 (@100MBit), does 0x0004 refer to the "2007" part and 0x0005 refer to the "2018" part?
    3. Can you expand on what you are observing when you say the Eth link connect/disconnect is detected? It sounds like you can establish link but link is dropped quickly. 

    We do not have test boards with the LPC2366 since we don't test all MACs with our PHY. 

    Have you checked for an errata regarding the LPC2366 since 2007? Is it possible that the pin states in processor have changed causing some different strapping behavior? 

    Based on the situation you've described the problem appears to be related to the processor and not the PHY. 

    Regards,

    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 40 points
    Dear Justin,
    Maybe you are aware of this problem :
    We have also some recent boards using LPC2378+DP83848, and we had to add a 115 Ohm in parallel with a 56pF capacitor, between pin25 of the PHY (25MHz_OUT) and the ground, to make the Ethernet work.
    So we have just done the same with our LPC2366 board, and now the processor is receiving correctly the ping frames at 100Mbit, transmit the ping answer to the PHY, but it doesn't seem to be transmitted to the network.
    Do you have any suggestion ?
     
    This afternoon, I will check registers 0x10 and  0x04 for both 2007 and 2018 processor.
     
    About the Eth link connect/disconnect, it works correclty, as we can see in the status register.
     
    Aboutthe NXP errata, they only talk about memory acceleration module, which could be slightly different in recent versions.
    Best regards
    Olivier
  • 0 in reply to olivier descoubes
    TI__Expert 7040 points

    Hi Olivier,

    If you could share your schematic that would be helpful in identifying a potential root cause. When sharing the registers, please indicate whether you are able to establish link and pass data or ping successfully for each setup.

    Regards,

    Justin 

  • 0 in reply to Justin Lazaruk
    Prodigy 40 points

    Hi Justin,

    We have connected the 50MHZ oscillator output direclty to the processor ethernet_clock_input  (instead of using the 25MHZ_OUT of the PHY), and it works fine now.

    It looks like the 'B' revision of the processor can work with the 25MHZ_OUT signal, whereas the 'D' revision of the processor can't.

    Thanks for your help !

    Regards

    Olivier