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DS90UB962-Q1: Some NG-item in D-PHY testing

Zhanpeng Li
Intellectual 2140 points
Part Number: DS90UB962-Q1


Hi team,

This is brandon. we were facing some problem in D-PHY testing. and hope you could help me.

[testing environment]

In the test network, the data of the external camera is input into Rin1 (or rin2) through fpd-link (the CMS / DMS of the two cameras correspond to different Rin1 / rin2 input test results are equivalent); then it is output to SOC through DSI.

The test clock is CSI_CLKN/P, and the data is CSI_D0N/P; see the attachment for the test report.

CSI1-Cms-datalp-clocklp-0420-NG.pdf

1)could you help analysis the reason of NG item and it would be great if you can provide with solution;

2)For Vcmtx in NG item, whether the floor with disty cause the reason;

3)For rise/fall time in NG item, can we adjust this specs by changing our device's driving way?

Thank you for your support.

BR

Brandon.

  • 0
    TI__Genius 11340 points

    Hi Zhanpeng,

    You're using 800Mbps/lane right? Normally there's no need to adjust the CSI timing, it looks like from your setup there's skew between data and clock -- this can cause timing issues.

    Please make sure the board is following the guidelines:

    • Route the CSI signals with 100ohm loosely coupled differential traces with tight impedance ±10%.
    • Pair-to-pair (ex. Data to CLK) spacing should be at least 3 times the trace width.
    • Pair-to-pair (ex. Data to CLK) length matching should be within 5 mils.
    • Intra-pair (P and N) spacing should be 2 times the trace width.
    • Intra-pair (P and N) length should be within 5 mils.
    • Implement loosely coupled serpentine for intra-skew length matching. Length tune near the mismatch if possible.
    • Use radius curves instead of 45 degree traces.

    And also make sure the probes you're using are of the same length.

  • 0 in reply to Jiashow Ho
    Prodigy 50 points

    Thank you for your reply.
    Yes,we're using 800Mbps/lane.

    I have a few more questions：

    1、Pair-to-pair (ex. Data to CLK) length matching should be within 5 mils？
    --》There's a principle we didn't follow. Our board Pair-to-pair length matching is 100mil.

    2、Resistance of CSI line is 0ohm，Is it necessary to change？ 

    3、We also use ds90ub941 too；the DSI Pair-to-pair (ex. Data to CLK) length matching should be within 5 mils？

    Best regards，

    Chen

  • 0 in reply to user4696789
    TI__Genius 11340 points

    Hi Chen,

    The 100mil length matching is most likely the cause of the issue. If the pair-to-pair length isn't within 5 mils of each other, then the data coming out of the CSI ports won't arrive at the processor at the same time. The CSI traces should be 100ohm differential. Same concept applies to the 941 as well.

    Best,

    Jiashow