SN65LVDS93A-Q1: SPREAD SPECTRUM CLOCKING - PLL limitations and modulation supported

typo SN65LVDS93A-Q1

Dear Support Team,

quick question  on SN65LVDS93A-q1. Customer needs to activate spread spectrum from uC, to lower the PCLK emissions, I wanted to know which is the limit for SSC for this device, it depends on the BW of PLL but in DS it is not specified.

Please let me know asap validation for final product EMI compliance

thanks

Kind Regards

Nicola

Hi Michael,

thanks! I somehow missed these parameters, sorry for the oversight!

thanks a lot

Nicola

Hi Michael,

just a very quick clarification: customer is double checking the definition of the spread spectrum modulation frequency that other competitors (from DSP side) define as actually half period of the triangular waveform, meaning that the frequency reaches max and min in one period (instead than in half period as i would expect).

Just to double check do we consider the entire period of triangular waveform correct? like here in fig 1 correct? http://www.ti.com/lit/an/spna090/spna090.pdf  

Thanks a lot

Kind Regards

Nicola