hi TI:
We use your sn65dsi86 chip (Mipi to EDP chip). The hardware eye map shows that the output EDP signal strength of sn65dsi86 is not enough.
How to modify the register to improve the EDP signal driving strength
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hi TI:
We use your sn65dsi86 chip (Mipi to EDP chip). The hardware eye map shows that the output EDP signal strength of sn65dsi86 is not enough.
How to modify the register to improve the EDP signal driving strength
Hi,
Please refer to Table 28 in the DSI86 datasheet, you can use the Table 28. CSR Bit Field Definitions—DP Link Training LUT to configure VOD, pre-emphasis, and post-cursor2 levels.
Thanks
David
hi David:
Table 28 has the following questions:
V0,V1in V0_P0_VOD and V1_P0_VOD indicate the driving intensity level. But I checked that the value of 0xc0 and 0xc1 registers is 0x3f, which means that V0, V1 and V2 are all open. Which level is currently used. If I turn on V3_P0_VOD, how to confirm that it is using V3_P0_VOD now
请问您会中文吗,如果会中文翻译如下;
表28有以下疑问:
V0_P0_VOD,V1_P0_VOD中的V0,V1是表示驱动强度等级。但我查看了0xC0,0xC1寄存器值都为0x3f,表示V0,V1,V2都有打开,那当前到底使用的是哪个等级呢。如果我把V3_P0_VOD打开,如何确认它现在用的是V3_P0_VOD
Hi,
You can use registers from 0xB0 to 0xBF to set the amplitude and pre-emphasis for each level.
Level 3 is disabled by default, but you can use registers from 0xC0 to 0xC3 to enable level 3 support option.
If training is successful, the SN65DSI86 will update the DP_POST_CURSOR2 (0x95, bit[3:1]), DP_PRE_EMPHASIS(0x93, bit[7:6]), and DP_TX_SWING(0x94, bit[1:0]) with the passing combination and then transition the ML_TX_MODE to normal.
You should also read registers from 0xF0 to 0xF8, and in particular 0xF8 to see if the link training is successful or not.
Thanks
David