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SN65DSI86: SN65DSI86 Display Port Test Pattern

Mark Chen52
Expert 8045 points
Part Number: SN65DSI86
Other Parts Discussed in Thread: TEST2

Hi Expert,

Customer would like to verify DP interface if product is embedded the DP port.

so they’d like to know how to control SN65DSI86 to test HBR, LBR, PRBS7, D10.2, and etc …? 

Could you help to comments?

Regards,

Mark

  • 0
    TI__Guru**** 178056 points

    Mark

    Please follow section 8.4.5.12 in the DSI86 datasheet. For compliance testing, please make sure both TEST2 and HPD pin are being pulled high.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    TI__Expert 8045 points

    Thanks David,

    Could you explain more detail for how to set register for DP compliance testing?

    For DP 1.2 compliance test (Physical Layer), we need set as below,

    Data Rate (1.62, 2.7, 5.4)

    HBR2

    HBR

    RBR

     

    Swing (0~3)

    400mV

    600mV

    800mV

    1200mV

     

    Pre-emphasis (0~3)

    0dB

    3.5dB

    6dB

    9dB

     

    Test Pattern

    PRBS7

    D10.2

    PCTPAT

    PLTPAT

    COMP

     

    For DP 1.2 compliance test (Link Layer)

    How to set Link Layer pattern?

    Regards,

    Mark

  • 0 in reply to Mark Chen52
    TI__Guru**** 178056 points

    Mark

    I sent you a DSI86 sample example code through direct email, please check.

    Can you please clarify your question on link layer DP1.2 compliance?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 10 points

    Hi David,

    This is MiTAC Marx.

    Let me consult some DSI86 DP questions.

    1. Does DSI86 support DP Physical Layer automation Test? (Use Unigraf DPR-100 + Keysight scope solution)

    2. Does DSI86 support D10.2 test pattern? We don't find it in datasheet. (Test pattern address 0x96)

    3. How to setting PLTPAT & PCTPAT pattern (Table 16) for standard DP compliance test?

    4. After TEST2 and HPD pin pulled high, does any other register need setting before do compliance test?

    Thanks!

  • 0 in reply to Marx Hsu
    TI__Guru**** 178056 points

    Hi,

    Please refer to section 8.4.5.12 DP Pattern of the DSI86 datasheet and the sample code I sent you earlier. Depending on the required data rate, SWIGN, Pre-emphasis, test pattern, you have to write to the appropriate DSI86 registers for the compliance testing. 

    D10.2 unscrambled is the same as TPS1. 

    For PLTPAT and PCTPAT, please use 80 bit Custom Pattern The 80-bit Custom pattern is used for generating the Post Cursor2 Test Pattern (PCTPAT) and the PreEmphasis Level Test Pattern (PLTPAT). The SN65DSI86 will continuously transmit the value programmed into the 80BIT_CUSTOM_PATTERN registers when the ML_TX_MODE is programmed to 80-bit Custom Pattern. The SN65DSI86 will always transmit over the enabled DisplayPort Lanes the LSB of the byte first and the MSB of the byte last. The byte at the lowest address is transmitted first.

    Thanks

    David