DP83867IR: This is in regard to Ethernet connectivity stability issues faced on transceiver [DP83867IR] for ongoing Bootloader project.

Ravishankar B M

Part Number: DP83867IR

Issue details:
We have configured the transceiver as per the attached configuration file.
As per the controller manual, the following extended registers to be configured in the transceiver initialization.
Eth_WriteMii( 0, 12, 0x0DU, 0x001FU); /*Register Control Register */
Eth_WriteMii( 0, 12, 0x0EU, 0x0032U); /* Address or Data Register */
Eth_WriteMii( 0, 12, 0x0DU, 0x401FU); /* Register Control Register */
Eth_WriteMii( 0, 12, 0x0EU, 0x0000U); /* Address or Data Register */
Eth_WriteMii( 0, 12, 0x0EU, 0x2100U); /* Address or Data Register */

/* CFG1 */
Eth_WriteMii(0,12,0x0009,0x0000);

After configuring the above registers, communication is established between Wireshark and Xilinx ECU. Ethernet Frames are observed in the Wireshark.
Here, we are facing the problem of network instability. Ethernet communication is loosing the connectivity frequently.

We are using Xilinx Evaluation board for our bootloader development. The DP83867IR transceiver used for the ethernet communication. We have configured the transceiver as specified in the transceiver specification document. The configuration list we had shared in the earlier email.

We used vector canoe tool and wireshark for the ethernet communication. The communication to the canoe is happened with 100MBPS and we found stable in network connectivity.
But our client requirement to connect with Wireshark. Here, we are facing the network instability issue (losing the network connection).
Configuration for both communication is same at the ECU/ transceiver Side.

We need support on DP83867IR programming

Hardware details – Do you have your own hardware that is using the TI SoC or this is on the TI EVM. Which SoC is this using?
• We are not having any specific ECU/Own hardware and we not using TI EVM.
• We are using Xilinx Zynq Ultrascale Evaluation board for our development activity. The Evaluation board contains TI DP83867IR transceiver for Ethernet communication.

Software details – what software deliverables are you leveraging from TI SDK deliverable? Please mention the SDK version as well.
• We are using the Xilinx SDK 2019.1

Note:
Tested with Auto Negotiation is enabled and disabled conditions.

Fullscreen EthTrcv.txt Download

/*******************************************************************************
**                      KPIT Technologies Limited                             **
**                                                                            **
** KPIT Technologies Limited owns all the rights to this work. This work      **
** shall not be copied, reproduced, used, modified or its information         **
** disclosed without the prior written authorization of KPIT Technologies     **
** Limited.                                                                   **
**                                                                            **
** MODULE   : EthTrcv.c                                                       **
**                                                                            **
** TARGET   : Not Applicable                                                  **
**                                                                            **
** PURPOSE  : Source File for EthTrcv                                         **
**                                                                            **
** PLATFORM DEPENDANT [yes/no]   : no                                         **
**                                                                            **
** TO BE CHANGED BY USER [yes/no]: no                                         **
**                                                                            **
*******************************************************************************/ 
#include <Eth.h>
#include <EthTrcv.h>

#define ETH_TRCV_IDX_12 12


void Eb_Intgr_EthTrcvInit_Initialization(const uint8 CtrlIdx)
{ 
uint8 EthTrcvIdx;
EthTrcvIdx = ETH_TRCV_IDX_12;

uint16 RegVal;

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 2, &RegVal); //read reg 2 val 0x2000

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 3, &RegVal); //read reg 3 val 0xa231

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 31, &RegVal); //read reg 31 val 0x0000

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 31, 0x8000); //write reg 31 val 0x8000

usleep(10);

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 31, &RegVal); //read reg 31 val 0x0000

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0, &RegVal); //read  reg 0 val 0x1140

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 0, 0x1140); //write  reg 0 val 0x1140

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x001F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x00FE);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0xe721); //write 254 val 0xe721

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 31, &RegVal); //read  reg 31 val 0x0000

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 31, 0x8000); //write reg 31 val 0x8000

usleep(10);

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 31, &RegVal); //read reg 31 val 0x0000

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 16, &RegVal); //read  reg 16 val 0x5048 

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 16, 0x5048); //write reg 16 val 0x5048

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 0x1E, 0x202); //write reg 0x1E val 0x0202

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0x1E, &RegVal); //read reg 0x1E val 0x0202

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x001F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0032);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_ReadMii( CtrlIdx, EthTrcvIdx, 14, &RegVal); //read reg 50 val 0x00d1
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x00D3); //write reg 50 val 0x00d3
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_ReadMii( CtrlIdx, EthTrcvIdx, 14, &RegVal); //read reg 50 val 0x00d3

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x001F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0086);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x00A9); //write reg 134 val 0x00a9

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x001F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0170);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_ReadMii( CtrlIdx, EthTrcvIdx, 14, &RegVal); //read  reg 0x170 val 0x0c0f
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0c1f); //write  reg 0x170 val 0x0c1f

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x001F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0172);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_ReadMii( CtrlIdx, EthTrcvIdx, 14, &RegVal); //read  reg 0x0172 val 0x0000
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F); 
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0006); //write  reg 0x0172 val 0x0006

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 24, 0x5160); //write reg 24 val 0x5160

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 1, &RegVal); //read reg 1 val 0x7949

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 15, &RegVal); //read reg 15 val 0x3000

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 4, &RegVal); //read  reg 4 val 0x01e1

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 4, 0x0181); //write reg 4 val 0x0181

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 9, &RegVal); //read  reg 9 val 0x0300

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 9, 0x0000); //write reg 9 val 0x0000

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0, &RegVal); //read  reg 0 val 0x1140

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 0, 0x1140); //write  reg 0 val 0x1140

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0, &RegVal); //read  reg 0 val 0x1140

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 0, 0x1340); //write reg 0 val 0x1340

usleep(50);

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0, &RegVal); //read reg 0 val 0x1140

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 1, &RegVal); //read reg 1 val 0x7949

usleep(80);

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 1, &RegVal); //read reg 1 val 0x796d

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 4, &RegVal); //read reg 4 val 0x0181

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 5, &RegVal); //read reg 5 val 0xcde1

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 9, &RegVal); //read reg 9 val 0x0000

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 10, &RegVal); //reg 10 val 0x0800


}


void Eb_Intgr_EthTrcvWaitLinkUp(const uint8 CtrlIdx)
{
  
  uint16 RegVal;
  uint8 EthTrcvIdx;

  EthTrcvIdx = ETH_TRCV_IDX_12;

  do {
  /** PHY register might take some time to update internal registers */
    Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0x11U, &RegVal);
  } while( (0x0400U & RegVal) == 0U);
}


void Eb_Intgr_EthTrcvInitRGMII(uint8 CtrlIdx)
{
	Eb_Intgr_EthTrcvInit_Initialization(CtrlIdx);
	Eb_Intgr_EthTrcvWaitLinkUp( CtrlIdx);
}

Fullscreen EthTrcv_1000Mbps.txt Download

/*******************************************************************************
**                      KPIT Technologies Limited                             **
**                                                                            **
** KPIT Technologies Limited owns all the rights to this work. This work      **
** shall not be copied, reproduced, used, modified or its information         **
** disclosed without the prior written authorization of KPIT Technologies     **
** Limited.                                                                   **
**                                                                            **
** MODULE   : EthTrcv.c                                                       **
**                                                                            **
** TARGET   : Not Applicable                                                  **
**                                                                            **
** PURPOSE  : Source File for EthTrcv                                         **
**                                                                            **
** PLATFORM DEPENDANT [yes/no]   : no                                         **
**                                                                            **
** TO BE CHANGED BY USER [yes/no]: no                                         **
**                                                                            **
*******************************************************************************/ 
#include <Eth.h>
#include <EthTrcv.h>

#define ETH_TRCV_IDX_12 12


void Eb_Intgr_EthTrcvInit_Initialization(const uint8 CtrlIdx)
{ 
uint8 EthTrcvIdx;
EthTrcvIdx = ETH_TRCV_IDX_12;

uint16 RegVal;

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 2, &RegVal); //read reg 2 val 0x2000

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 3, &RegVal); //read reg 3 val 0xa231

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 31, &RegVal); //read reg 31 val 0x0000

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 31, 0x8000); //write reg 31 val 0x8000

usleep(10);

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 31, &RegVal); //read reg 31 val 0x0000

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0, &RegVal); //read  reg 0 val 0x1140

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 0, 0x1140); //write  reg 0 val 0x1140

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x001F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x00FE);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0xe721); //write 254 val 0xe721

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 31, &RegVal); //read  reg 31 val 0x0000

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 31, 0x8000); //write reg 31 val 0x8000

usleep(10);

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 31, &RegVal); //read reg 31 val 0x0000

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 16, &RegVal); //read  reg 16 val 0x5048 

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 16, 0x5048); //write reg 16 val 0x5048

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 0x1E, 0x202); //write reg 0x1E val 0x0202

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0x1E, &RegVal); //read reg 0x1E val 0x0202

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x001F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0032);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_ReadMii( CtrlIdx, EthTrcvIdx, 14, &RegVal); //read reg 50 val 0x00d1 Getting 0x00d0
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x00D3); //write reg 50 val 0x00d3
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_ReadMii( CtrlIdx, EthTrcvIdx, 14, &RegVal); //read reg 50 val 0x00d3

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x001F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0086);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x00A9); //write reg 134 val 0x00a9

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 16, &RegVal); //read  reg 16 val 0x5048

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 16, 0x5048); //write reg 16 val 0x5048

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x001F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0170);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_ReadMii( CtrlIdx, EthTrcvIdx, 14, &RegVal); //read  reg 0x170 val 0x0c0f Getting 0x0c0e
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0c1f); //write  reg 0x170 val 0x0c1f

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x001F);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0172);
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F);
Eth_ReadMii( CtrlIdx, EthTrcvIdx, 14, &RegVal); //read  reg 0x0172 val 0x0000
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 13, 0x401F); 
Eth_WriteMii( CtrlIdx, EthTrcvIdx, 14, 0x0006); //write  reg 0x0172 val 0x0006

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 24, 0x5160); //write reg 24 val 0x5160

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 1, &RegVal); //read reg 1 val 0x7949  Getting 0x796D

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 15, &RegVal); //read reg 15 val 0x3000

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 4, &RegVal); //read  reg 4 val 0x01e1

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 4, 0x01e1); //write reg 4 val 0x01e1

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 9, &RegVal); //read  reg 9 val 0x0300

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 9, 0x0200); //write reg 9 val 0x0200

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0, &RegVal); //read  reg 0 val 0x1140

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 0, 0x1140); //write  reg 0 val 0x1140

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0, &RegVal); //read  reg 0 val 0x1140

Eth_WriteMii( CtrlIdx, EthTrcvIdx, 0, 0x1340); //write reg 0 val 0x1340

usleep(50);

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0, &RegVal); //read reg 0 val 0x1140

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 1, &RegVal); //read reg 1 val 0x7949 Sometimes getting 0x796D

usleep(80);

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 1, &RegVal); //read reg 1 val 0x7969 Getting 0x796D

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 4, &RegVal); //read reg 4 val 0x01e1

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 5, &RegVal); //read reg 5 val 0xc1e1 Getting 0xcde1

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 9, &RegVal); //read reg 9 val 0x0200

Eth_ReadMii( CtrlIdx, EthTrcvIdx, 10, &RegVal); //reg 10 val 0x2800 Sometimes getting 0x3800


}


void Eb_Intgr_EthTrcvWaitLinkUp(const uint8 CtrlIdx)
{
  
  uint16 RegVal;
  uint8 EthTrcvIdx;

  EthTrcvIdx = ETH_TRCV_IDX_12;

  do {
  /** PHY register might take some time to update internal registers */
    Eth_ReadMii( CtrlIdx, EthTrcvIdx, 0x11U, &RegVal);
  } while( (0x0400U & RegVal) == 0U);
}


void Eb_Intgr_EthTrcvInitRGMII(uint8 CtrlIdx)
{
	Eb_Intgr_EthTrcvInit_Initialization(CtrlIdx);
	Eb_Intgr_EthTrcvWaitLinkUp( CtrlIdx);
}

0381701_HW-Z1-ZCU102_REVC_SCHEMATIC_20160105_102759_wm.pdf

over 5 years ago

0 Justin Lazaruk over 5 years ago

TI__Expert 7040 points

Hello Ravishankar,

Thank you for reaching out. I will take some time to review the register data and schematic you provided and will be able help debugging the DP83867 link quality in the next week.

Regards,
Justin

0 Justin Lazaruk over 5 years ago in reply to Justin Lazaruk

TI__Expert 7040 points

Hi Ravishankar,

Thank you for taking time to share a debugging session to determine the root cause. I am closing the e2e post after our offline debug session.

Wireshark and Vector Canoe were able to transmit frames in 100Mbps mode after refining the register settings.

Regards,
Justin

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DP83867IR: This is in regard to Ethernet connectivity stability issues faced on transceiver [DP83867IR] for ongoing Bootloader project.