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SN65DSI84: SN65DSI84 Application Question

user5956241
Intellectual 565 points
Part Number: SN65DSI84
Other Parts Discussed in Thread: DSI-TUNER

Hi TIer,

After I initialized the register according to the DSS, if I judge the A.7 (PLL LOCKED) bit, I find that it will never be set to 1, which means there is no way to LOCK  problem?  ? 

I 'm design  REF CLK connected to 36MHz active crystal.

  • 0
    TI__Mastermind 35130 points

    Hi John,

    Your pixel/line settings are incorrect. All of the line parameters should be the same value for both the DSI side and the LVDS side.

    For the pixel parameters, each DSI pixel parameter should be double that of each LVDS pixel parameter.

    Additionally, your DSI clock should be 432 MHz, not 427.3488 MHz. It's important that the frequency is precise as the DSI84 does not realign timing. 

    In regards to your question, the DSI-Tuner does not enable the PLL since it needs to be enabled manually in accordance to the initialization sequence. The PLL is enabled by writing 1 to register 0x0D. Please make sure that you follow the initialization sequence in the datasheet.

    Regards,

    I.K.

  • 0 in reply to Ikechukwu Anyiam
    TI__Mastermind 35130 points

    Also, it looks the DSI-Tuner window is getting cut off. Please use this version of the tool instead - it should fix that:

    1401.DSI Tuner 2.1.zip

    Regards,

    I.K.