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DS90UB960-Q1: FPD Link layout routing layer and refernece layer questions

user5977574
Prodigy 135 points
Part Number: DS90UB960-Q1

Hi guys,

here is a question about 960 FPD Link routing. Do you have a case that routing FPD Link signal lines in the inner layer? If yes, could you share this experience?

If no case routing inner layer, if we routing FPD Link signal lines in the inner layer, which layer is as its reference layer?(Note: our board is 14 layers, top and bottom  layer can't routing these lines. and according to the big PoC current capability, routing FPD Link adjacent layer will be cut off to keep its impendence and current requirement, so, FPD Link will be compartment reference). And for  FPD Link signal lines, how many reference layers should be to FPD Link? 

  • 0
    TI__Mastermind 30515 points

    Hi,

    For FPD-Link high speed trace, it is recommended that the stripline is used if the trace is >2inches for better system level EMI performance. so it is ok in your case, you can use the next layer as reference GND, in the turn-over, you can use more GND vias close to this area for continuous GND. 

    Steven

  • 0 in reply to Steven(Shenzhen) Shi
    Prodigy 135 points

    Hi steve

    Thanks for your reply. Is any other use case routing in the inner layer for FPD-Link III and FPD_LinkIV?

    So, you mean that for FPD-Link III, we route in the inner layer is ok? just can use one next layer as the refernece GND. Do it need two layers  as reference GND/Power(Adjacent up and down layer)?

    Another question is if for FPD_LinkIV, what about its routing in inner layer comments?

  • 0 in reply to user5977574
    TI__Mastermind 30515 points

    Hi,

    FPD-Link III data rate is up to ~3.3Gbps, you can use stripine, generally one reference GND is used.

    For FPD-Link IV, since the rate is much higher, generally to get better SI performance you can try to reduce the vias and try to short the PCB trace between the high speed pins and connector, typically 1-2inches. the longer the trace, the worse the SI performance, this would impact your high speed link jitter margin.

    regarsds,

    Steven