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DS90UB954-Q1: The last 3 lines of sensor0/1 captures are interchanged when use 954/954

Lei
Prodigy 205 points
Part Number: DS90UB954-Q1

Dear Team,

Our system and configure information as below.

and the detail register as below

7a 01 02
SL 100

7A 0c cf
7A 10 91
7A 11 85
7A 13 89
7A 14 8d

;fps
7A 19 0c;frame sync=25Hz, BC_FREQ_SELECT=24MHbps,20200414
7A 1a 7f;32000*0.1-1=3199,
7A 1b 70;
7A 1c 7f;((3199+1)/0.1)*0.9-1=28799
;7A 18 01; enable FSIN, internal FSIN. enabled in another configure file.

7A 1f 02; Backchannel 25M,MIPI OUTPUT =800M,default value is 800M,20200414.

7A 4c 01 ;SELECT PORT0
;7A 58 5e ;Enable I2C Pass Through
7A 58 5d ;Enable I2C Pass Through,back channel changed to 24Mbps,20200414
7A 5c 32 ;Serializer Alias
7A 5d 60 ;native I2C ID
7A 65 68 ;Imager alias


7A 6D 78 ;Set to STP mode
7A 6E A0 ;BCC GPIO1 select frame sync signal
7A 70 2B ;RAW10 DT + VC0
7A 71 2C ;RAW12 DT + VC1
7A 72 E8 ;VC Mapping default - vc0


7A 4c 12 ;SELECT PORT1
;7A 58 5e ;Enable I2C Pass Through
7A 58 5d ;Enable I2C Pass Through,back channel changed to 24Mbps,20200414
7A 5c 34 ;Serializer Alias
7A 5d 60 ;native I2C ID
7A 65 6a ;Imager alias


7A 6D 78 ;Set to STP mode
7A 6E A0 ;BCC GPIO1 select frame sync signal
7A 70 6B ;RAW10 DT + VC0
7A 71 6C ;RAW12 DT + VC1
7A 72 ED ;VC Mapping default - vc1

7A 33 03 ;CSI Continous clock + 4 Lanes
7A 20 00 ;Forward all RX to CSI0

SL a0

34 0b 20 ;I2C speed: 390K
34 0c 20
34 02 53 ;MIPI 2lane; 73: 4lane
34 06 81 ;refclk to sensor:24MHz.954_REF_CLK=24MHz from OV491, so HS_CLK_DIV =16,M=1,N=5;-----20200413
34 07 05 ;0x06 and 0x07 used for setup pll for output clock for sensor, clock_out= REFCLK_954*80*M/(N* HS_CLK_DIV)

SL 20
32 0b 20 ;I2C speed: 390K
32 0c 20
32 02 53 ;MIPI 2lane; 73: 4lane
32 06 81 ;refclk to sensor:24MHz.954_REF_CLK=24MHz from OV491, so HS_CLK_DIV =16,M=1,N=5;-----20200413
32 07 05 ;0x06 and 0x07 used for setup pll for output clock for sensor, clock_out= REFCLK_954*80*M/(N* HS_CLK_DIV)

SL 60
34 0e F0 ;[7:4]: enable GPIO0/1/2/3 output
32 0e F0 ;[7:4]: enable GPIO0/1/2/3 output
34 0d 20 ;enable FSIN remote control
32 0d 20 ;enable FSIN remote control
SL 20
34 0d 21 ;01: OV TI953 board; 04: TI daughter board
32 0d 21 ;01: OV TI953 board; 04: TI daughter board
SL 20
34 0d 29 ;03: OV TI953 board; 0C: TI daughter board
32 0d 29 ;03: OV TI953 board; 0C: TI daughter board
SL 20
32 0d 2D ;set 953_0 gpio2 to 1, so red led on.-----------20190702

We found a strange issue when we power on our system. Mostly the capture is OK, but occasionally, the last 3 lines  of sensor0/1 captures are interchanged after power on. We are sure that the last 3 lines are changed with left capture and right capture. We can see the data by FPGA, and you can see it as below

We changed the 954_REF_CLK from ISP to 25MHz， and changed the other related registers, there is no  any effort.

We changed the BC datarate from 24Mbps to 48Mbps(954_REF_CLK  is 24Mhz), and the FC datarate from 1920Mbps to 3840Mbps, and changed the other related registers, the issu seems been solved.

But we also want to use the half FC frequency(1920Mbps) , because there is lock link errors when FC datarate is full frequency(3840Mbps).

Could you help we analyze this issu?

Thanks.

  • 0
    TI__Expert 3390 points

    Hi Lei,

    To summarize and make sure I understand the issue. The last few lines (up to 3) end of up shifting slightly during power up and the issue is intermittent. Also, the issue goes away when you run the Forward Channel at ~4G instead of ~2G and setting the BC to ~50Mbps instead of ~25? You still prefer to use the 2G Forward Channel.

    I have some further questions, if you haven't tried the items below, can you please do so and get back to me on the results?

    1) Do you see the issue when you run a single sensor?

    2) Do you see the issue when you don't use FrameSync and forward the CSI data to the SoC with Round Robin Best Effort?

    3) Do you see the issue when you use PatGen on both serializers?

    4) To clarify, you are combining the 2-lane CSI Input from both imagers and forwarding from the 954 as 4-lane CSI output. Correct?

    Regards,
    Mandeep Singh

  • 0 in reply to Mandeep S
    Prodigy 205 points

    Hi, Mandeep 

    We will do some test follow your suggestion, but it require some time.

    And there is a new information to share with you.

    We changed the 954 register 0x21 to value 0x14 follow the code example as below.

    We found the issue disappeared.

    We can't understand it, and don't know if it will bring some new issues.

    Thanks.

  • 0 in reply to Mandeep S
    Prodigy 205 points

    Hi, Mandeep

    Correct your understanding about this issue.

    When appear this issue after power on, it will be error all the time, not intermittent. It can be resolved by system soft reset.

    Thanks!

  • 0 in reply to Lei
    TI__Expert 3390 points

    Hi Lei,

    Do you have any further questions regarding this topic? It seems like the issue is fixed if you use basic sync forwarding. I'm not sure what was the original forwarding method but seeing that basic sync forwarding fixes the issue means that the SoC is having issues handling the incoming CSI data in the original forwarding method.

    Regards,

    Mandeep Singh