Other Parts Discussed in Thread: TCAN4550, TCAN4550-Q1
Hello,
I have an FPGA board connected to the TCAN4550 EVM. The FPGA controls and talks to the TCAN directly w/o a CPU. I've used the TCAN software example and wrote the HDL based off of it.
Everything works from the RX and TX prospective. I can receive pkts into the the FPGA's SRAM and send out pkts from the FPGA SRAM. The issue I'm seeing is CANSLNT errors in the 8 bit status returned from TCAN during the TCAN command 32 bit phase. I'm not using wake and I'm not using the sleep mode so these are disabled based on the eval HW and SW selection.
0800h is set for 080004A2h, so the wake config is disabled/00, WD_EN is a 0, MODE_SEL is normal/10. The other reg configuration are per the example code. I'm not wait but more than 30sec or so to start transmission both ways.
I have searched and read the other CANSLNT related posts and didn't see anything to me that would be similar. Any ideas to go about debugging this?
Thank You,
Greg Holdren
Motion Control Engineering