SN65DSI86: FPGA + MC20902 solution issue

Hi,

Agree that eDP side looks OK given that the color bar now is working. 

Have you cleared the errors at register 0xF0 first and then read the register again? I want to make sure the errors being reported are real errors. If the errors are real, then this indicates a potential signal integrity issue on the DSI interface.

With a scope, please make sure the setup and hold timing meet the requirement as listed in the DSI86 datasheet.

You can also try to change the RX equalizer at register 0x11 and see if it helps.

Thanks

David

Hi, David, thank you for your reply.

David (ASIC) Liu said:

Have you cleared the errors at register 0xF0 first and then read the register again?

Yes, I cleared the errors at 0xF8 register, and error 0x3 appears again after next reading

David (ASIC) Liu said:

this indicates a potential signal integrity issue on the DSI interface

What kind of integrity issue? On my PCB lanes from MC20902 bridge to DSI86 has few inches length (1.0-1.5 approx), and I have no abnormal things in signal waveform. But maybe I violate time constrains.

David (ASIC) Liu said:

You can also try to change the RX equalizer at register 0x11 and see if it helps.

It has no effect

I tried to skip setting the register 0x12 to value of 100 and after reboot I saw 99 in it, which means that the DSI86 correctly detected the frequency value, but still no data recognized.

Please look at my waveform SoT sequence, is it correct?

Yellow - hs clock

Blue - hs positive data

In the near future, we will be able to examine the signals more accurately when we have a wider bandwidth oscilloscope.

Hi,

Please refer to Figure 4, DSI HS Mode Receiver Timing Definitions for the timing definition. Both Tsetup and Thold timing must be minimum of 0.2UI.

If the timing is correct, then can you please check to see if the MC20902 is sending the commands that are being supported by DSI86? Section 8.4.4.2 lists the DSI Supported Data Types, all other non-supported data types will be ignored by DSI86.

Thanks

David

David (ASIC) Liu said:

Please refer to Figure 4, DSI HS Mode Receiver Timing Definitions for the timing definition. Both Tsetup and Thold timing must be minimum of 0.2UI.

How can I find out other parameters in terms of specification MIPI D-PHY, such as TCLK-SETTLE, THS-SETTLE, etc..? They are not listed in the datasheet. Have you more information about timing requirements for DSI86?

I need to know what THS-PREPARE/THS-ZERO/THS-SETTLE timing intervals I must provide in my DSI transmitter 

The DSI86 will following the MIPI D-PHY spec timing requirement and ignore any data lane HS transitions and only respond to the HS transition after the max THS-SETTLE. The most important timing is the setup and hold timing requirement to make sure the data is being clocked correctly into the DSI86.

Thanks

David 

David, I checked setup/hold times on my DSI lanes with wide bandwith oscilloscope and it is equal about 300+ps, and meets the DSI86's requirements of 0.2UI (200ps@500MHz ).

Have you any ideas?

Can I see the actually received data by DSI86 in TI test registers page?

I have a small transient spike when switching to hs- mode, can it have a negative effect?

The received data is not available inside the DSI86. Can you check to see if the MC20902 is sending the commands that are being supported by DSI86? 

Thanks

David

MC20902 is simple voltage translator/mux and does not perfom any logical functions. All packets generated by fpga, and I check it in my fpga design, but I don't understend why DSI86 cannot receive sync sequence 0xB8

If I send one short packet only, can dsi86 accept it? Then I will check error registers for SOT errors

You can use the Generic Short Write with 2 parameters to write to SN65DSI86 CFR registers. The first parameter is the CFR Address and the second parameter is the data to be written to the address pointed to by the first parameter. 

Thanks

David

Thanks, it is good idea, I will try it and report the results few days later

Thank you very much, David, this article helped me a lot. I found an error in my sync sequence. I would like not to close this topic until I debug my video stream completely

Hello, team

I corrected my sync sequence and there are no more errors in register F0, but I have a next question about DSI-side of SN65DSI86.

An error appeared in register F6 - 0x40 (LOSS_OF_DP_SYNC_LOCK_ERR).

I configured the GPIO2 and GPIO3 pins to output VSYNC and HSYNC, respectively, and I see on the oscilloscope that the these pulses are generated correctly.

My DSI86 is now clocked from an external 27MHz clock. The DSI frequency of the stream is 500 MHz.

Please help me in finding the reason for the out of sync with the DisplayPort sync generator, what do I need to adjust in the DSI stream?

UPD:

I found that the GPIO3 (HSYNC) pin contains only pulses in vertical blanking period (when DE is inactive) (32 pulses).

Do I understand correctly that I should see pulses in the period of active video?

Hi,

Please check DSI86’s video registers from 0x20 thru 0x3A to make sure the video timing programming into the DSI86 registers matches with the timing received on the DSI interface.

Thanks

David