SN65HVD96: Power over data issues

Rafa Crespi

Part Number: SN65HVD96

Hi,

We are developing new product based on SN65HVD96 and Power over data application note http://www.ti.com/lit/an/slla336/slla336.pdf?&ts=1588921006385 and it's not working.

We have based our design in the one in Figure5.

We have two testing boards (Find schematic attached):

- We are injecting square wave on D pin of the first one to simulate transmission frame.

- On second board we are receiving wavecorrectly until R pin is reached, there wave is lost.

We have tried to using 120 ohm resistor as described in Figure5, but not working too.

If we use asymmetric wave it works fine.

We have tested with square wave frecuency range between 4 - 30KHz

200508_SFBUS_test.pdf

Rafa

over 5 years ago

0 Miguel Robertson over 5 years ago

TI__Guru 62920 points

Hi Rafa,

So that we can better understand the application, could you please show us the waveforms at the A and B inputs of the receiving SN65HVD96 for the symmetrical- and asymmetrical-wave cases?

Regards,
Max

0 Rafa Crespi over 5 years ago in reply to Miguel Robertson

Prodigy 80 points

Hi Max,

Red -> R of receiving SN65HVD96

Yellow -> AB of receiving SN65HVD96

Asymmetric Input:

Symmetric input:

It seems like R is detecting AB edges....

Kind Regards,

Rafa

0 Miguel Robertson over 5 years ago in reply to Rafa Crespi

TI__Guru 62920 points

Hi Rafa,

I suspect the difference is due to the the different test patterns resulting in different DC bias levels detected at the differential input of the HVD96 device. With a symmetrical pattern the waveform will be "centered" after the AC-coupling capacitances so that the high and low extremes are above the "active" input threshold and the transitions pass through the "passive" threshold region. With an asymmetrical repetitive pattern the effective DC level shifts, and in this case it must make it so only the low signal periods result in differential voltage magnitudes greater than the "active" threshold.

Regards,
Max

0 Rafa Crespi over 5 years ago in reply to Miguel Robertson

Prodigy 80 points

Hi Max,

With your explanation along with https://e2e.ti.com/support/interface/f/138/t/666038, I think I have understood what is happening.

We need use it with symmetrical signals, so....Maybe the solution would be implementing a Tri-level transmitter just as in Fig.9 of

https://www.ti.com/lit/an/slla336/slla336.pdf?&ts=1589270021519

It is right?

Kind Regards,

Rafa

0 Miguel Robertson over 5 years ago in reply to Rafa Crespi

TI__Guru 62920 points

Hi Rafa,

Using tri-level transmission will help, but it wouldn't totally resolve the potential issue of the data pattern containing so many "0" bits in a row that the voltage at the receiver (post-AC-coupling) decays back to a "passive" level. This is mentioned briefly on page 8 of the app note you linked. A solution would be to run at a higher baud rate, use larger L/C coupling values, or to introduce some level of software coding that intersperses "1" bits regularly in the datastream.

May I contact you privately via email? I have an alternative approach I would like to propose but is not ready to be disclosed publicly.

Regards,
Max

0 Rafa Crespi over 5 years ago in reply to Miguel Robertson

Prodigy 80 points

Hi Max,

Ok, thanks for information. I will study it

Of course, my email is rafa@ibercomp.com

Kind Regards,

Rafa

Interface

Interface forum

SN65HVD96: Power over data issues