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DP83867E: DP83867 SGMII NO LINK

Part Number: DP83867E

Hello,

Switch and PHY 83867 interface are SGMII, switch-> PHY is tested by Digital Loopback, I can link up to detect link status is also set, but after closing loopback, the link has not been connected, the initial problem may be PHY-> RJ45-> PC, I would like to ask you which PHY-> RJ45-> PC, which registers do I need to operate?

THANKS 

Best regards!

  • Hello,

    Can you provide more information about the test that you are running? What strap configuration are you using, you can use registers 0x006e and 0x006f to confirm your desired strap configuration is being latched during start-up or reset. 

    Register 0x0001 can be used to determine the status of the Link and Auto-Negotiation as well. 

    Regards,

    Justin 

  • Hi Justin,

    Thank you for your reply quickly! I have dumped all the PHY registers -including the ones you asked me.

    DP83867ERGZ  100Mbps, Full Duplex, SGMII Auto-Negotiation,Mirror Enable
    STRAP PIN 
    RX_CTRL MODE4
    GPIO_0   MODE1
    GPIO_1   MODE1
    LED_2   MODE1
    LED_1   MODE1
    LED_0   MODE4
    PHY Reg: 0x0  Read: 0x3100
    PHY Reg: 0x1  Read: 0x7949
    PHY Reg: 0x2  Read: 0x2000
    PHY Reg: 0x3  Read: 0xa231
    PHY Reg: 0x4  Read: 0x1e1
    PHY Reg: 0x5  Read: 0x0
    PHY Reg: 0x6  Read: 0x64
    PHY Reg: 0x7  Read: 0x2001
    PHY Reg: 0x8  Read: 0x0
    PHY Reg: 0x9  Read: 0x1300
    PHY Reg: 0xa  Read: 0x0 
    PHY Reg: 0xf  Read: 0x3000
    PHY Reg: 0x10  Read: 0x5C48
    PHY Reg: 0x11  Read: 0x6002
    PHY Reg: 0x12  Read: 0x0
    PHY Reg: 0x13  Read: 0x40
    PHY Reg: 0x14  Read: 0x29c7
    PHY Reg: 0x15  Read: 0x0
    PHY Reg: 0x16  Read: 0x0
    PHY Reg: 0x17  Read: 0x40
    PHY Reg: 0x18  Read: 0x6160
    PHY Reg: 0x19  Read: 0x4440
    PHY Reg: 0x1a  Read: 0x2
    PHY Reg: 0x1e  Read: 0x2
    PHY Reg: 0x1f  Read: 0x0
    PHY Reg: 0x25  Read: 0x0
    PHY Reg: 0x2d  Read: 0x0
    PHY Reg: 0x31  Read: 0x6002
    PHY Reg: 0x32  Read: 0x0
    PHY Reg: 0x37  Read: 0x40
    PHY Reg: 0x43  Read: 0xA231
    PHY Reg: 0x6e  Read: 0x0
    PHY Reg: 0x6f  Read: 0x3000
    PHY Reg: 0x71  Read: 0x6002
    PHY Reg: 0x72  Read: 0x0
    PHY Reg: 0x86  Read: 0x64
    PHY Reg: 0xd3  Read: 0x40
    Thanks,Look forward to receiving your reply!
    Best regards!
    peng
  • Hi Peng,

    I will take time to review your register data and aim to provide a response by 5/19. Thank you for you help in resolving this.

    Regards,
    Justin 

  • Hi Peng,

    It appears that the straps circuitry you are using is not strapping the desired values into the PHY. For example:

    Register 0x006E bit 15 = 0 meaning Mirror Mode is strapped to Disable. LED_0 Mode 4 is not a valid strap setting, please use Mode 3 to enable Mirror Mode.

    Register 0x006E bit 7 = 0 meaning Auto-Negotiation is strapped to Enable. RX_CRTL Mode 4 strap is not disabling Auto-Neg.

    Try fixing these settings and observing whether that allows you to get link.

    Regards,
    Justin 

  • Hi Justin,

    Thanks again for your reply. As you said, I have changed the mode of RX_CRTL to 3 to enable auto-negotiation. And register 0x0000(BMCR) is 0x1140, auto-negotiation is enabled. 

    The MAC connected to 83867 is switch89551. I want to do a digital loopback from MAC 89551-> PHY-> MAC 89551. So I set port 6 of 89551 to SGMII, auto-negotiation mode, 100M, full duplex. But this digital loopback has never worked. Rgister 0x0011(PHYSTS) is 0x0002,bit 15:14 =0 meaning speed is 10M,bit 13=0 meaning half duplex. Digital Loopback is no success.

    If i closed Auto-negotiation, force speed 100M, mode is full duplex. MAC 89551->83867->MAC 89551 Digital Loopback is success.

    Register 0x0031(CFG4) is 0x1002. And I cannot modify  this register?

    Register 0x0037(SGMII_ANEG_STS) is 0x0040. Bit 0 = 0 meaning SGMII Auto-Negotiation process not complete.Bit 1 = 0 meaning SGMII page has not been received. How should i do ?

    This is my hardware schematic.

    Thank you very much for taking the time to help solve this problem.

    Best Regards,

    Peng

  • Hi Justin,

    Awaiting for your reply.

    As this issue is very critical to us,I request you to reply at your earliest convenience.

    Thanks and Regards,

    Peng

  • Hi Peng,

    There is a note in the datasheet in section 8.4.4.1 stating that Auto-Negotiation must be disabled for Near-End loopbacks, that includes digital loopback mode. If you want to continue using loopback modes with Auto-Negotiation enabled, please use an external loopback.

    Regards,
    Justin 

  •  Hi Justin,

    Thank you for your support.

    I have considered using external loopback before, but SGMII does not support external loopback.

    The purpose of doing loopback is also to verify MAC-> PHY-> RJ45-> PC step by step. Now i close AUTO-NEGOTIATION,  the digital loopback is success, which means that MAC-> PHY is no problem.

    When i close digital loopback,MAC->PHY->RJ45->PC is not link up.

    Register 0x0001(BMSR) is 0x7949, bit 2 (0) meaning link not established.

    Can you please let us know,what other things can be checked.

    Thanks and Regards

    Peng

  • Hi Peng, 

    I want to confirm that you have updated the RX_CRTL strap from the schematic above and register 0x0000=1140?

    What is driving your need for Mirror Mode? I may have been mistaken above, in SGMII mode Mirror Mode is enabled in mode 3 & 4; your schematic shows Mirror Mode enabled. If you disable mirror mode through registers or strap, are you able to get link? This can be changed in register 0x0031[0]

    Regards,
    Justin 

  • Hi Justin,

    I have updated the RX_CRTL from mode 4 to mode 3, read register 0x0000 = 0x1140.

    =================================================================

    If you disable mirror mode through registers or strap, are you able to get link?

    ================================================================

    Now my LED_0 use mode 4, Mirror Mode is enable, but read register 0x0031(CFG4) is 0x6B02, bit 0 is 0. And 0x006E is 0x0000, bit 15 meaning port mirroring strapped to disable.Do you have any advices?

    Considering that it may be the cause of RJ45, remove RJ45 from the hardware and connect directly with network cable,but still no link.

    Thanks and Regards,

    Peng

  • Hi Peng,

    The value of the SOR register still does not match your desired strap conditions. Is the external connection on LED_0 driving the pin low when the straps are being latch on power-on or reset?

    Can you also describe why you desire Mirror Mode? Based on your schematic, where you have channel A from RJ45 connector to channel A of PHY, Mirror Mode will incorrectly expect channel A of the RJ45 to connect to channel D of the PHY.

    Regards,
    Justin 

  • Hi Justin,

    Thanks for your lots of suggestions.This problem is indeed caused by the mirror enable. After we disable the Mirror Mode, the link succeeds.

    Thanks and Regards,

    Peng