TFP410-EP: TFP410 DE Generator

Dear Sir,

May i get your email id for further discussions ?

Hi Shekhar,

It is better to ask your questions here so that other people that may have the same question can see them. 

Regards,

I.K.

Hi Sir,

I have TFP410 interfaced with Zynq UltraScale+ chip.

So, my video source is the Zynq, So will this have a DE signal ?

Else we need to configure through I2C, If then, could you please provide i2c software .c file for below specification ?

RES = 720x480p

Blanking = 25%

Hi Shekhar,

You'll need to check with Xilinx or go through that chip's datasheet to confirm whether or not it has a DE signal. 

Also, we don't provide code for the TFP410. Since the configuration is only through pin-strapping or I2C, you can go through the register map or pin descriptions in the datasheet and check what settings you need to configure.

Regards,

I.K.

Hi Sir,

Thank you for your inputs.

The TFP410 requires a reset after power up, so if i do reset i.e SEL/RST# low to high, then I2C is selected and chip configuration is set based on the configuration bits (BSEL, DSEL, EDGE) and state bits (PD, DKEN) in the I2C registers

Now I have to configure the I2C registers for my 24bit, single-edge, rising, single ended clock mode.

Then what is the use of hard-wiring on boards these pins, which are of no use when I power cycle [OFF -> ON] ?

Hi Shekhar,

Please see the descriptions for these pins in the Pin Functions table in the datasheet. It describes their use when I2C is enabled/disabled.

It's a lot easier to configure the device through pin-strapping rather than through I2C, so I recommend verifying whether or not your source generates DE.

Regards,

I.K.

Hi Sir,

So as far i understand, below is the functional sequence [assuming SCH is correct]

• Power-On the board
• Hard-Wired
  • A3,A2,A1 -> GND [I2C addr = 0x70,0x71]
  • MSEN -> Only providing Test Point
  • ISEL/Rst# -> Pull down [Connected to FPGA also]
  • BSEL/SCL -> pull-high [24bit data]
  • DSEL/SDA -> pull-up [Since vref = vdd, this DSEL shall be independent to our design, single ended clock]
  • EDGE -> pull-high [rising edge]  
  • DKEN -> pull down [default trim]
  • Vref = DVDD
  • PD# -> pull high
• ISEL initially would be low, drive from FPGA a low to high transition [I2C is selected]
  • With this the chip gets power-on-reset
  • Now only configure DE generator related registers
    • CTL_1_MODE to CTL_3_MODE -> Not configured [Dependent on hard wiring]
    • DE_DLY, DE-CTL, DE-TOP, DE-CNT, DE-LIN -> Configured as per our 720x480, Blanking = 25%

• Now ISEL is pulled low by FPGA, all the configuration happens through pin-strapping, and now the 24-bit pixel_data is sent w.r.t IDCK+ and the data is observed on DVI monitor

Please provide your feedback on our approach

PS: Soon shall share with the I2C register values for DE generation

That looks okay. Don't forget to set the polarity of HSYNC/VSYNC in DE_CTL.

Regards,

I.K.

Hi

Actually I got to know that we are generating DE Generator from our Zynq FPGA

Sowe shall only use ISEL/rst for power on reset and then pull it down for pin strapping.

Still do we need to configure few resistors via I2C ??

Hi Shekhar,

No, you don't need to use the I2C interface if your FPGA is generating DE.

Regards,

I.K.

Hi

Thank you, but how come the chip knows my HSYNC, VSYNC polarity

And If I need DDC signals to the DVI Monitor from this chip, how shall I interface?