DS90UH947-Q1: control signal communication between 947/948 when 1.LVDS 2.PCLK interrupt

Roy Chou1

Part Number: DS90UH947-Q1

Hi Team,

I would like to know if I use 947/948 for SerDes

1. If the 947LVDS data is interrupt for 1ms, but PCLK is maintain. Whether the control signal in FPD-link will continue to communicate each other or not.

2. If the 947LVDS data and PCLK are interrupt for 1ms. Whether the control signal in FPD-link will continue to communicate each other or not.

Regards,

Roy

over 5 years ago

0 Casey McCrea over 5 years ago

TI__Guru** 103215 points

Hello Roy,

For #1 there will be no interruption in the FPD-Link so long as the clock remains stable

For #2 there will be a temporary interruption in the FPD-Link during the clock glitch

Best Regards,

Casey

0 Roy Chou1 over 5 years ago in reply to Casey McCrea

TI__Genius 16110 points

For #2

Do we have corresponding buffer to handle the signal like I2C while LVDS/PCLK absent? Maybe re-send or any error handling to the signal?

Regards,

Roy

0 Casey McCrea over 5 years ago in reply to Roy Chou1

TI__Guru** 103215 points

Hello Roy,

If the PCLK input goes away, then there will be a temporary link interruption, but the FPD-Link will automatically switch over to internal clock in order to drive the link for basic communications functionality like I2C. Is this what you are looking for?

Best Regards,
Casey

0 Roy Chou1 over 5 years ago in reply to Casey McCrea

TI__Genius 16110 points

Hi Casey,

Yes, I'm looking for this, could you provide me some APP note if we have?

Regards,

Roy

0 Casey McCrea over 5 years ago in reply to Roy Chou1

TI__Guru** 103215 points

Hello Roy,

I'm sorry but there is no app note specifically for this. The clocking is described in the 947 datasheet

Best Regards,

Casey

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DS90UH947-Q1: control signal communication between 947/948 when 1.LVDS 2.PCLK interrupt