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TL16C550D: Data buss state at Reset condition

Part Number:

Hi Expert,

My customer have some questions about TL16C550D,

Question1,

Could you please let me know the data buss state at Reset condition?

(e.g, High-Z?)

Question2,

If TL16C550D resisters  will be accessed at reset condition, What value would the device return?

(e.g. In case of Data buss is high-Z, it is depend on external pullup.)

Thanks

Muk

  • Hey Muk,

    Yusuke Mukuno said:

    Part Number: TL16C550D

    Hi Expert,

    My customer have some questions about TL16C550D,

    Question1,

    Could you please let me know the data buss state at Reset condition?

    (e.g, High-Z?)

    [Bobby] You mean when you hold the device in reset (reset held HIGH and NOT toggled)?

    Question2,

    If TL16C550D resisters  will be accessed at reset condition, What value would the device return?

    (e.g. In case of Data buss is high-Z, it is depend on external pullup.)

    [Bobby] The parallel interface (D0-D7) and serial interface (Tx) are push pull so you should not require pull up resistors on the bus. Are you asking about series resistors in the case where the lines are NOT HI-Z when reset is held HIGH?

    Thanks

    Muk

    Please see my comments above.

    -Bobby

  • HI Bobby-san,

    Thank you for your reply.

    For Question1, Yes it is meaning when  MR pin is held high.

    For Question2, sorry for your confusion. customer question is

    If TL16C550D will be accessed any communication from other device when the MR pin is held HIGH, How will the state of parallel interface (D0-D7) and serial interface (Tx) look from other device?

    Thanks

    Muk

  • Hi Bobby-san, thank you for your reply

    I'm sorry to say that TL16C550DPT datasheet shows

    [Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, D4 47 and status information between the ACE and the CPU.]

    and SC16C550B (NXP) datasheet shows

    [Data bus. Eight data lines with 3-state outputs provide a
    bidirectional path for data, control and status information
    between the UART and the CPU.]

    Please make sure which is correct answer, push/pull or 3-state outpus.

    And I'd like to know the behavior during resetting.

    Best regard,

    Tomo

  • Hey Tomo,

    Apologies I've been out of the office.

    I believe the parallel lines are supposed to be HI-Z (3-state as you put it) when the device is held in reset however to try to confirm this, I've reached out to someone in our design team to see if they can double check this. I'll see if I can get an answer from him by tomorrow.

    -Bobby

  • The design engineers got back to me today. It looks like they can't help verify this in a design sim so this means I will need to place an order for a breakout board and samples of the device to verify for you. I should have an idea of when I can test this in the lab by next week.

    -Bobby

  • Bobby-san,

    Ok, we wait your answer. We would like to get your answer as soon as possible. sorry to bother you,

    I summarized about customer 3 question, again.

    Question1
    Could you please let me know the data buss state when MR pin is held high?

    Question2
    If TL16C550D will be accessed any communication from other device when the MR pin is held HIGH, How will the state of parallel interface (D0-D7) and serial interface (Tx) look from other device?


    Question2
    Please make sure which is correct answer, push/pull or 3-state outputs.

    Thanks

    Muk

  • Bobby-san

    Do you have any update?

    Thanks

    Muk

  • Muk,

    I've place an order for sample devices and a breakout board to test them. I am still waiting to receive them.

    -Bobby

  • Bobby-san,

    Do you have any update? Can you get the test board?

    Muk

  • Hey Muk,

    I went into the office Thursday to see if the breakout board came, turns out it wasn't delivered. I pinged our Admin who placed the order to contact the supplier and heard back that they were delayed in shipping it so it ended up shipping on Friday instead. I've received the breakout today (need to double check if its correct) and will see if I can submit a soldering request to a lab tech, after that is finished I should be able to verify for you. I expect I should be able to have results by end of day Friday at the latest (and earliest is tomorrow if the soldering request is finished in time).

    -Bobby

  • Muk,

    I've got the boards back from the solder technicians. I'll see if I can make the measurements for you this weekend since this has been in the queue for quite a while.

    Sorry for the delay,

    -Bobby

  • Muk,

    I was able to run my tests today and I found that the parallel data pins are only HI-Z if the read select pins is inactive, even when the device is in reset if RD1 or RD2 are active then the D0-D7 pins will drive the line.

    Thanks,

    -Bobby

  • Hi,  Bobby and Muk,

    Thank you for your help.

    I could solve the problem.

    Take care, Tomo