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SN65DSI84: Cannot output test pattern to our 1920 x 1080 panel

Mark Chang
Prodigy 30 points
Part Number: SN65DSI84
Other Parts Discussed in Thread: DSI-TUNER

Hello experts,

Our NXP i.MX8MQ project uses the SN65DSI84 to convert MIPI to LVDS signals.

We tried to use DSI_Tuners to generate all register setting and enable Reg-3ch = 0x10 to output test pattern, but it failed and the Reg-e5 = 0x7d.

We also tried to use DSICLK and REFCLK to do the same test, but the test pattern cannot be outputed to panel.

Could please help to review our settings.

(1) Is it correct for AU-M215H 1920 x 1080 panel parameters? (http://www.bfdisplay.fr/fiches-techniques/ecrans-tft/AUO%20-%20M215HTN01_V1.pdf)

LVDS_HPW = 2

LVDS_HBP = 74

LVDS_HFP = 14

LVDS_VPW = 2

LVDS_VBP = 36

LVDS_VFP = 12

(2) Using DSI_Tuner to generate SN65DSI84 register settings.

SN65DSI84_DSI_Tuner_Conf.zip

SN65DSI84_Registers.zip

3058.sn65dsi84_test_m215h.zip

M215HTN01.1.pdf

Regards,

Mark

  • 0
    TI__Mastermind 35130 points

    Hi Mark,

    Looking at your DSI-Tuner settings, your DSI-CLK is way too fast. Your DSI CLK should be 444 MHz for these settings.

    Please also ensure that you are enabling the PLL in register 0x0D as this needs to be done manually.

    Regards,

    I.K. 

  • 0 in reply to Ikechukwu Anyiam
    Prodigy 30 points

    Hello I.K.,

    Thanks for your reply.

    Could please help me to review my test script?

    6327.sn65dsi84_test_m215h.zip

    The first command and last command are as below:

    echo "Set reg-09h to 01h"
    i2cset -f -y 2 0x2c 0x09 0x01
    sleep 0.1

    echo "Set reg-0Dh to 00h"
    i2cset -f -y 2 0x2c 0x0D 0x00
    sleep 0.1

    ...

    ...

    echo "Set reg-0Dh to 01h"
    i2cset -f -y 2 0x2c 0x0D 0x01
    sleep 0.1

    echo "Set reg-09h to 00h"
    i2cset -f -y 2 0x2c 0x09 0x00
    sleep 0.1

    Regards,

    Mark

  • 0 in reply to Mark Chang
    TI__Mastermind 35130 points

    Hi Mark,

    You still need to update the clock settings as mentioned above.

    Regards,

    I.K.

  • 0 in reply to Ikechukwu Anyiam
    Prodigy 30 points

    Hello I.K.

    I tried to measure the MIPI DSI CLK_p signal.The clock rate is 240MHz.

    It seems the DSI CLK will be 480MHz. Is it right?

    But the test pattern still cannot be outputed.

    Do you have any suggestion for us?

    Thanks for your great support.

    CSR_DSI_480MHz_20200522.txt 
    //=====================================================================
// Filename   : CSR_DSI_480MHz_20200522.txt
//
//   (C) Copyright 2013 by Texas Instruments Incorporated.
//   All rights reserved.
//
//=====================================================================
0x09              0x00
0x0A              0x05
0x0B              0x2a
0x0D              0x00
0x10              0x26
0x11              0x00
0x12              0x60
0x13              0x00
0x18              0x6f
0x19              0x00
0x1A              0x03
0x1B              0x00
0x20              0xc0
0x21              0x03
0x22              0x00
0x23              0x00
0x24              0x38
0x25              0x04
0x26              0x00
0x27              0x00
0x28              0x21
0x29              0x00
0x2A              0x00
0x2B              0x00
0x2C              0x02
0x2D              0x00
0x2E              0x00
0x2F              0x00
0x30              0x02
0x31              0x00
0x32              0x00
0x33              0x00
0x34              0x4a
0x35              0x00
0x36              0x24
0x37              0x00
0x38              0x0e
0x39              0x00
0x3A              0x0c
0x3B              0x00
0x3C              0x10
0x3D              0x00
0x3E              0x00


The PLL_EN bit and SOFT_RESET bit are not set as they need to be set per the recommended sequence defined in the datasheet

    Regards,

    Mark