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DP83867CS: CLOCK OUT question

Lee Stevens
Prodigy 120 points
Part Number: DP83867CS

The default CLOCK OUT is set at the input clock at 25MHz. We have this PHY connected to an NXP T2081. The T2081 seems to require the CLOCK OUT to be 125MHz. This has been my experience with all the GbE designs I've ever done. How can we get the PHY to produce a constant 125MHz for the MAC?

  • 0
    TI__Genius 9920 points

    Hello,

    Thank you for your interest in our device and submitting this question. The DP83867 has a register configuration Reg 0x0170 which lets you configure the clock out. Selecting any of the transmit clocks should provide you the 125MHz you need.

    Thanks,

    Cecilia

  • 0 in reply to Cecilia Reyes
    Prodigy 120 points

    Thank you Cecilia,

    We did try that and it worked, temporarily. We are concerned about how robust this solution would be in a real environment like VxWorks or Linux. After making that change in U-boot, we downloaded Linux, booted Linux and it changed the clock frequency back to 25MHz and would no longer transmit data.

    Are you suggesting we make the change in U-boot, Linux and VxWorks drivers?

    Lee

  • 0 in reply to Lee Stevens
    TI__Genius 9920 points

    Hi Lee,

    There may be something in the drivers that change the default setting of the clock output to 25MHz. You may need to make those changes in the driver to incorporate the register write. 

    Thanks,

    Cecilia