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DP83867IR: Occur CRC Error between DP83867 PHYs

seokyeon kim
Prodigy 10 points
Part Number: DP83867IR


I developed product using DP83867.

It works properly at most time, but sometimes there is CRC error between products.

When CRC Errors occurs, after re-link up or re-power cycle, then it works well again.

For debug this issue, I checked PHY's status register and I found some weird status.

BSMR(addr: 0x0001) Bit 2 indicates Link status and PHYSTS(addr: 0x0011) Bit 10 also indicates Link Status

But those register bits show different between status each other when CRC Error occurs.

BSMR bit 2 is 0(Link not establiched) and PHYSTS bit 10 is 1(Link is up)

Is it possible status? What can I do for correct this weird status with out re-link up or re-power cycle?

- Link speed was 1000M(1G) and VDDIO was 3.3V. It means RGMII Interface line also operates under 3.3V power rail.

  • 0
    TI__Genius 9920 points

    Hello thank you for sharing your status with the DP83867.

    Can you please provide these registers when it is working properly and when you start seeing the CRC errors?

    Have you tried resetting the device by writing to reg 0x001f = 0x4000 to do a software reset? 

    Thanks,

    Cecilia

  • 0 in reply to Cecilia Reyes
    Prodigy 80 points

    Hello,

    Yes I have tried resetting the device using reg0x001F = 0x4000

    Then, link partner start relink and after second link, CRC problem has beed fixed.

  • 0 in reply to Cecilia Reyes
    Prodigy 80 points

    Yes, after SW_Restart, relink has executed, and no more CRC error occured.

    Cecilia Reyes said:

    Hello thank you for sharing your status with the DP83867.

    Can you please provide these registers when it is working properly and when you start seeing the CRC errors?

    Have you tried resetting the device by writing to reg 0x001f = 0x4000 to do a software reset? 

    Thanks,

    Cecilia

    Yes, after SW_Restart, relink has executed, and no more CRC error occured.

  • 0
    Prodigy 80 points

    Yes, after SW_Restart, relink has executed, and no more CRC error occured.

  • 0 in reply to sykim
    TI__Genius 9920 points

    Ok, please let me know if you need further assistance or if this resolves your issue.

  • 0 in reply to Cecilia Reyes
    Prodigy 80 points

    It is fortunate that the situation in which the CRC occurs is resolved by SW restart, but further analysis is needed for the condition in which the CRC occurs.

    What I want is to not link up with CRC occurring.

    Could you offer suggestions to me what can I do to prevent from CRC errors occurring? 

    Also, it is necessary to review how to take care when bit 2 of BSMR and bit 10 of PHYSTS are different. Is it normal status that the corresponding registers have different values?

  • 0 in reply to sykim
    TI__Genius 9920 points

    Hello,

    Bit 2 for this status is a latch low, which is why you may see a link not established. You need to read this register twice to clear and give you the correct read.

    Bit 10 will give you the real time link status which is why you are seeing the link up.

    Some issues you can target as a source of the error could be clock input quality or cable length. When you are seeing the CRC errors, can you also share the XI clock signal quality? Can you please also share the cable length you are using for these tests?

    Thanks,

    Cecilia