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XIO2001: Bridge not found. PCI_CLK distortion.

Josh VanDeMark
Prodigy 50 points
Part Number: XIO2001

Currently developing the XIO2001 to replace a design going EOL. Having difficulty troubleshooting the XIO2001. Attached are a few oscilloscope images (A) PCI_CLK (B) Power-up sequence.

A. Below is an image of the PCI_CLK. This signal is present at both PCI slots as well as the PCI_FBCLK. We have the EVM so I know the negative swing of the CLK is expected, but not the distortions.

B. Below is the power-up sequence. Yellow = 1.5Vdc. Cyan = nGRST. Magenta = nPERST. Lime = REFCLK+.

I believe the oscillation seen on the 1.5Vdc rail at the beginning of REFCLK+ is a probe grounding issue and not the coupling of REFCLK+ to the power rail.

Based on my understanding, these are in order and the minimum timing requirements are greatly exceeded.

I have a hunch the board house did not properly perform requested impedance matching as they also changed our requested copper thicknesses.

What could cause the distortions on PCI_CLK? Would the distortions on the CLK prevent the XIO2001 from being discovered by the PC? Additionally, could this also prevent the PC from booting? Half of the ordered boards do not allow the PC to boot.

I would be more than happy to share schematics or board layout via email. Any help or input will be greatly appreciated.

Thank you.

  • 0
    Prodigy 50 points

    I now see that nGRST is de-asserting at the same time as the power rails are coming up which could put the XIO2001 in an unknown state.

    Any ideas why this may be? Could this cause the distortions on CLK?

  • 0 in reply to Josh VanDeMark
    TI__Expert 8135 points

    Hello-

    Are you using a probe with a long GND lead to probe the CLK signal?  The CLK signal does not look too bad, so it is unlikely cause of issues.  The measurement could improve if the probe GND lead is very short (~1 cm).

    An incorrect power-up sequence could be a cause of issues.

    Also, ensure PLL power is isolated from other supplies.  The device needs very clean power rails, especially the PLL.
    Regards,
    Davor
  • 0 in reply to Davor Glisic
    Prodigy 50 points

    Davor,

    Thank you for your response. I was initially using a long GND cable. After some research I ended up winding wire around the ground contact at the end of the probe with a length of about 1-2 cm.

    How would you suggest we slow down nGRST? I was thinking an RC, but without knowing the value of the internal resistor I am going to have to make assumptions and try different caps.

    PLL is isolated and appears clean. I have attached a screen capture for the power portion of the schematic.

    I have also attached updated startup sequence captures. The time base was removed from the images due to it covering waveforms, but the zoom factor, etc. is at the top of the images. I have verified that REFCLK comes up 4.2ms before nPERST, and nGRST de-asserts 192ms before nPERST. However, it does appear that nGRST de-asserts before PCIR is valid and settled.

  • 0 in reply to Josh VanDeMark
    Prodigy 50 points

    PCIR is connected to the 5V rail, but the 1k and .1uF cap seem to be creating an RC delay. Before modifying the suggested values for PCIR, could I connect the 5V supply to an external source so that 5V and PCIR are high when the XIO2001 initializes? Just to test the theory that the start-up sequence is the issue.

  • 0 in reply to Josh VanDeMark
    TI__Expert 8135 points

    You probably want to disconnect / disable your 5V on-board source before connecting an external supply.

    Regards,

    Davor