I'm using DS90UB926 and 925 chip set and seeing a issue with the i2c bus giving me a false response or maybe it is a response based on not up and running yet . From what I can tell if I change the i2c register settings in the 926 or set the 925 and 926 to low speed mode and send a packet to the 926 so it can pass it over the link to the 925 or slave device on the 925 the 926 will respond with a nack right away for all slave devices that are not the 926. I'm sending the i2c packets back to back with no delay between the 926 reg config and the slave write packets for the other side of the link. I have enclosed a pic that show the write to the 926 in this case address 0x58 then I write to register 0x02 and set it to 0x03 (low speed mode) then send to a slave device 0x6c I see the nack happen with out delay. If you look at the next packet that address the same slave device at 0x6c it takes about 163ms for this response and the same time for all the other responses. I see this same thing if I set the 926 to i2c pass through reg 0x05 to 0xae then try to read from the 925 reg it will give me ack right away but if the link is up and I don't write to this read and access the 925 it takes time for the ack to get set.
Is this a known behavior? If so what is the delay I need to wait between setting the reg on the 926 and then trying to use the i2c bus? It would be nice to have a value and not just guess to make sure I get good results across all my boards.
One other question what is the difference between setting the I2C pass through mode bit 3 of reg 03 in the 926 and i2c pass through all bit 7 of reg 05?
