DS280DF810: How to thru the input data?

Hi,

• What data rate are you trying to operate in?
• What is the retimer input channel and output channel insertion loss?
• Related to: "But my environment doesn't work well"
  
  • Can you provide more clarification as to what that means? Are you able to see retimer data output?

Upon first review your retimer script for CDR bypass looks reasonable. Two comments below.

1. Whether the EQ setting is optimal depends on the retimer input channel insertion loss in your system
2. Empirically TI typically observes best performance with eq_hi_gain=1 and vga_sel_gain=0

Regards,

Rodrigo Natal

HSSC Applications Engineer

Hi Rodrigo,

Thanks for your reply.

• What data rate are you trying to operate in?

->Now I input 10Gbps signals because I don't have high speed pattern generator more than 20Gbps so far.

   I understand this device can receive only more than 20Gbps, so I'm trying with raw mode.

   Later I'll change my instrument to 25Gbps.

• What is the retimer input channel and output channel insertion loss?

  -> insertion loss should be no problem.

      Input/output trace on PCB is quite short.

      Anyway I'll check S11 of input trace.

• Related to: "But my environment doesn't work well"
  
  • Can you provide more clarification as to what that means? Are you able to see retimer data output?

  ->No, output signal looks fixed (I don't know high or low because of AC coupling).

      I can see just quite small noise.

1. Whether the EQ setting is optimal depends on the retimer input channel insertion loss in your system
2. Empirically TI typically observes best performance with eq_hi_gain=1 and vga_sel_gain=0

-> you mean the registers 0x13[5] and 0x8e[0]?

    I'll try to change them.

If you have suggestions or advices, please let me know.

Can you try forcing signal detect asserted on the retimer channel in question by setting channel register 0x14[7]=1, and checking whether you are able to observe data output with CDR bypass enabled?

Hi Rodrigo,

my update is here.

1. input/output trace looked good

2. EQ and VGA gain didn't affect

3. write 0x14[1]=1 also didn't affect, and this register could follow correctly  if signal was applied to Rx or not

4. output noise was changed by CDR mux mode (mute or raw)

   -> 0x1e[7:5]=0x7(mute) is clean

        0x1e[7:5]=0x0(raw mode) is a bit noisy

        0x1e[7:5]=0x1~6(undefined) is so noisy

        Can they mean the MUX and Driver work correctly?

I'm suspecting FIR is not correct, but I wonder what setting is correct for FIR.

Now only main cursor is enable(0x3d = 0x1a), because pre/post cursor can't work due to no recovered clock.

Can you advice me?

I don't understand your results. If you are inputting a 10G signal to the retimer then you should be able to observe that same signal at the retimer output while operating in CDR bypass mode if you have set it correctly. When the retimer is set to bypass mode the FIR settings should not have effect. The retimer operates at a fixed output amplitude when CDR bypass mode is enabled, and pre-cursor and post-cursor EQ functions do not do anything.

How are you implementing the retimer? Are you using TI evaluation board or some system application board? If using the TI evaluation board I would recommend to use the TI SigCon Architect GUI, which may be downloaded via TI.com.

Rodrigo

OK, I misunderstood FIR behavior because TX FIR is next stage of MUX.

I'm using our own board, not TI evaluation board.

I re-confirmed the pin-assign of layout, and it was correct (I believe this should be OK because sigdet worked and noise was changed by mux setting)

For less than 10Gbps, can CDR lock correctly? if so, I'll try retimer mode.

Also if you have any control sequence as a reference, could you share with me?

OK, I'll try with Quarter-rate mode.

I'm referring DS2x0DFxx0_SNLU182E_Programmers_Guide_Confidential_20180814_APL.pdf.

Do you mean this document?

Hi Rodrigo,

sorry for my late reply.

My original sequence referred Table79 in SNLU182E_Programmers_Guide, but didn't work.

Let me summarize current situation.

1. 10MHz clock can be observed at power-on

=> output connection is good (at least low frequency signal can thru)

2. SIGDET register (0x01[7]) can assert when signal is applied to input port

=> input connection is also good

3. toggling DRV_PD register (0x15[3]) and SEL_DATA_PRELCK(0x1e[7:5]) affects output signal only for a moment

=> channel selection is good

4. even SD_ENABLE(0x95[7]) = 1, output is still stable (clock signal is applied to the input)

Do you have any other suggestions?

And you said FIR function didn't affect under raw mode, but it should work because FIR decides the output amplitude, I think.

(but my device never outputs even when I changed FIR registers...)

Thanks,

Hi Rodrigo,

Finally I found some clues.

- to enable MUX before FIR, 0x09[5] needs to be 0

Table30 of programmers guide has a typo

- to change the mux, cal clock is needed

once the mux setting is done, the clock can stop

Now raw mode works well.

I'm still working to understand what condition is good for CDR lock.

For 300Mbps clock pattern, default setting is enough to lock. But higher datarate doesn't work.

If you know this phenomenon is reasonable, please let me know.