DP83867E: :

Onur Kusakoglu

Intellectual 965 points

Part Number: DP83867E

Hi,

What is the internal pull-up and pull down resistor values of DP83867E component?

Best Regards

over 5 years ago

0 Vikram Sharma over 5 years ago

TI__Genius 16030 points

Hello,

9K +/- 25% (part to part variation).

Regards,

Vikram

0 Onur Kusakoglu over 5 years ago in reply to Vikram Sharma

Intellectual 965 points

I would like to start the PHY at powered down status and let my FPGA decide to enable it.

As far as I understand, after power-up these pull-up on Interrupt/ Power-down pin will be disabled.

Until that time, there will be a conflict on this pin because it will be pulled down, externally and pulled-up internally.

To beat the internal pull up I need to place a smaller value resistor to pull it down. Do you have any recommendation for this?

Best Regards,

Onur

0 Onur Kusakoglu over 5 years ago in reply to Onur Kusakoglu

Intellectual 965 points

And one other thing I would like to clarify, we don't do any strapping for the interface type, only for address. And our interface will be RGMII. Is it OK by power up? We will configure the PHY via register based on the interface setting. Do you think this approach is totally fine?

0 Onur Kusakoglu over 5 years ago in reply to Vikram Sharma

Intellectual 965 points

Same question is valid also for reset pin. It has an internal pull up but I would like to connect a pull down resistor to reset pin to keep it at reset state until FPGA release the reset. Any blocking item for me to add a pull down by default? and any resistor value recommended?

Best Regards

Onur

0 Vikram Sharma over 5 years ago in reply to Onur Kusakoglu

TI__Genius 16030 points

Hi Onur,

Sorry for the delay. I am discussing the constraints internally and will get back to you by 12th June.

Regards,

Vikram

0 Vikram Sharma over 5 years ago in reply to Vikram Sharma

TI__Genius 16030 points

Hi Onur,

After power up of the phy internal pull ups of 9K on pwdn and resetn pins are always enabled. So if you put a pull-down to make these inputs low, they will always stay low. Can you put an active switch to drive the level low of these pins when you want to keep them low?

Phy will power up fine in Rgmii mode and you need not write a regiter for sgmii or rgmii mode. But there is a note in datasheet which mandates the strap on rx_cntrl pin : See table 5 : 4-level strap pins. If you dont have the required strap then you need write a register as mentioned in the note below table 5.

Regards,

Vikram

0 Onur Kusakoglu over 5 years ago in reply to Vikram Sharma

Intellectual 965 points

Hi,

I saw it in the data sheet. But as far as I understand this is valid for only SGMII interface. Should I also put this strap pins to RX_Control pin for RGMII interface?

If it is valid and recommended for both RGMII and SGMII interfaces then I prefer to add these resistors to RX_Control pins.

Best Regards,

Onur Kusakoglu

0 Vikram Sharma over 5 years ago in reply to Onur Kusakoglu

TI__Genius 16030 points

Hi Onur,

I will re-check and confirm if it is only applicable to Sgmii mode. Did you see it any app note that strap on rx_ctrl can be ignored if in sgmii mode?

Regards,

Vikram

0 Vikram Sharma over 5 years ago in reply to Vikram Sharma

TI__Genius 16030 points

Please do the required register write( if not using rx_cntrl strap resistor ) for both sgmii and rgmii mode.

Regards,

Vikram

0 Onur Kusakoglu over 5 years ago in reply to Vikram Sharma

Intellectual 965 points

I added the strap resistor and set it to mode-3 just in case.

Onur

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