DS90UB954-Q1: Any suspect reason Lock established but no output at 954 side?

Hello Alex,

Please make sure you forward the RX port to the CSI-2 output port using register 0x20 and enable the CSI-2 output in 0x33

Best Regards,

Casey 

Hi Casey,

The design uses 954 RX0.

954: 0x20 = 0x20

954: 0x33 = 0x23

My understanding is as long as link established (Lock keep high) 954 MIPI outout would reproduce 953 MIPI input. Is this correct?

Regards,

Alex

Hello Alex,

Can you check registers 0x73-0x76 on the 954 to see if it is detecting valid video input?

Best Regards,

Casey  

Hi Casey,

0x73 = 0x01
0x74 = 0xE0
0x75 = 0x07
0x76 = 0x80

Line count = 480

Line length = 1920

Regards,

Alex

Hello Alex,

Ok, then I don't see any reason why there would be no CSI-2 output from 954. Have you verified by probing the CSI-2 lanes on the 954 to see if they are toggling?

Best Regards,

Casey 

Hi Casey,

I am now remotely helping RnD debugging. Will visit on-site to verify the waveform on 954 end. 

So from the 0x73-0x76, there is valid video input to 954, and 0x02 = 0x1E means CSI2 output control no problem. 

It should be not possible 954 not output right?

What if the CSI input to 953 exceeds the 953 FC data rate limitation of 3.2Gbps? 

Regards,

Alex

Hello Alex,

Is anything else being programmed besides what you shared? Based on the configuration of only register 0x02, 0x20, and 0x33, there should be no issue. 0x73-0x76 indicate that there is video being received so I believe it should be coming to the CSI-2 output correctly. You can verify it with a scope. 

If you are using 25Mbps back channel as per your first message, then the FC rate will be 24MHz*80 = 1.92Gbps in synchronous mode and the max CSI-2 bandwidth is 24MHz*64 = 1.536Gbps

With CSI-2 input of 400Mbps/lane, 2 lanes there will be no issue with the 953 CSI-2 input. If the data rate exceeds 1.536Gbps on the 953 input in this scenario, you will start seeing CSI-2 line length unstable errors on the 954 most likely. 

Best Regards,

Casey 

Hi Casey,

Thanks!

RnD says the image resolution is sent to 953 with 1920x1080/30fps. Does it meets the Line count/length reported by 954?

I found the 954 0x4E = 0xFD which indicates the "LINE_LEN _UNSTABLE" = 1. Do you think RnD might made wrong setting to CIS? 

Regards,

Alex

Hello Alex,

No, the registers indicate the incorrect line count (480). Also what is the data format? (bits per pixel and CSI-2 code)

Best Regards,

Casey 

Hi Casey,

The CIS output data type is RAW10. (CSI code 2B and10bits per pixel).

We also find 953 0x5E = 0x44 shows CSI data lane0/1 error.

RnD has verified skip 953/954, the video can be displayed at processor side.

Regards,

Alex

Hi Casey,

Some I2C communication problem found at 953.

1. It's looks like a clock stretch problem.

2. RnD said the sensor ID is 16bits format, and SOC will judge whether it get the correct sensor ID. If the ID correct, the following sensor initialization will no problem. Otherwise, the sensor initial will failed.

From the this I2C communication, does 953 can accept 16bits read data and send to 954 with no problem?   

Regards,

Alex

Alex,

I'm not sure what you are trying to show with the above picture. 954 and 953 can support 16 bit addressing without any issue and also I2C clock stretching is normal/expected when communicating across the control channel like this

Can the customer confirm the sensor configuration by reading back all the programmed registers to confirm that they were programmed correctly? Does the I2C master support I2C clock stretching?

Best Regards,

Casey