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DS280DF810: How to support up to 28.4Gbps?

yang qiang
Prodigy 40 points

Part Number: DS280DF810

I'm testing with DS280DF810, using manual data rate configuration, and found the chip can only lock to data rate up to 26.5625G.

When setting to higher data rate such as 27.9525/28.2Gbps, the CDR lock status is unstable, after a while(1 min something), the CDR perform unlock status. also the eye figure is totally lost.

So, any other Reg need to be operated?

Setting as below:

WriteToDS250DF810(DS250DF810ADDR,0x60,80,1); //28.2Gbps

WriteToDS250DF810(DS250DF810ADDR,0x61,C6,1);

WriteToDS250DF810(DS250DF810ADDR,0x62,80,1);

WriteToDS250DF810(DS250DF810ADDR,0x63,C6,1);

WriteToDS250DF810(DS250DF810ADDR,0x64,0xFF,1);

WriteToDS250DF810(DS250DF810ADDR,0x09,0x04,1);

WriteToDS250DF810(DS250DF810ADDR,0x18,0x00,1);

WriteToDS250DF810(DS250DF810ADDR,0x0A,0x0C,1);

WriteToDS250DF810(DS250DF810ADDR,0x0A,0x00,1);

  

  • 0
    Prodigy 40 points

    After more detail study/test:

    If the Crosspoint function is enabled(A->B, B->A), the 28.2G is much more difficult to lock. Some channel will show unlock status randomly.

     

  • 0 in reply to yang qiang
    TI__Mastermind 19235 points

     

    Your channel register settings look correct. Some debug questions below:

     

    1. Could you provide a description of your DS280DF810 retimer test setup?

      • A block diagram would be useful

      • If you can provide estimate retimer input channel insertion loss value, that would also be helpful

    2. Could you provide values for the following retimer channel registers when the 28.2G CDSR lock issue is observed? If possible please capture these retimer register values for both case when CDR is locked as well as CDR unlocked

      • 0x02, 0x27, 0x28, 0x8F