DP83867IS: About reset problem of PHY chip (DP83867ISRGZ)

Le Qi

Part Number: DP83867IS

Our laboratory is using TI's PHY chip (DP83867ISRGZ) as the network interface part of FPGA. We would like to confirm whether the reset of the 43rd pin must be done to pull down 1us after power on? If the pin remains high after power-on, will it cause the PHY chip to work abnormally?

over 5 years ago

0 Justin Lazaruk over 5 years ago

TI__Expert 7040 points

Hello Li,

The RESET pin on the DP83867IS is an active low pin, meaning that pulling the RESET pin low will cause the part to go into Reset. The 1us spec in the datasheet states that if you would like to reinitialize the part, you must hold RESET low for 1us before releasing and allowing pin to be pulled high again.

When the RESET pin is set high the part remains in normal operation. There is an internal pull-up on this pin to ensure the pin is held high unless driven low by application, and your pull-up in the schematic above follows our layout guidelines.

Regards,

Justin

0 Le Qi over 5 years ago in reply to Justin Lazaruk

Prodigy 20 points

Thank you very much for your help, so is it necessary for us to pull down the reset pin 1us every time after the hardware is powered on, then pull it up, then configure the PHY chip through mdio?

Because our hardware board has design flaws, we cannot control the level of the reset pin, so this reset pin is pulled high at any time. Does this mean that we lack the reset that we should have at power-on and cause abnormal operation?

0 Justin Lazaruk over 5 years ago in reply to Le Qi

TI__Expert 7040 points

Hello Li,

No, you do not have to pull down the reset pin after power on. You will be able to communicate with the PHY through MDIO after power on.

Further you can reset the device through register 0x001F if desired as well.

Regards,

Justin

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DP83867IS: About reset problem of PHY chip (DP83867ISRGZ)