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LMH1297: Errors and signal loss with pathological signal

TISL
Expert 4750 points
Part Number: LMH1297
Other Parts Discussed in Thread: SIGCONARCHITECT

Dear e2e support,

My customer is facing some errors and signal loss when 12G pathological signals are used with our LMH1297 (prototype board or EVM).

The signal is generated by a Phabrix QX. They use 1m cables from Belden (1694A) and HUBER+SUHNER Coaxial Cable Connector (11_BNC-75-5-20/133_N).

Below are his screen shots.

Would you have any idea where the issue comes from?

Regards,

  • 0
    TI__Guru* 93570 points

    Greetings TISL,

    Does your customer sees similar issue at longer cable length like 30 or 50m?

    Regards,, Nasser 

  • 0 in reply to Nasser Mohammadi
    TI__Expert 4750 points

    Hi Nasser,

    The result is worst with a 40m cable.

    Regards,

  • 0 in reply to TISL
    TI__Guru* 93570 points

    Hi TISL,

    Please ask your customer to change SigconArchitect Output Mux Selection drop down menue - note middle right hand side of the SigconArchitect GUI image -  to independent control like what i have shown below. This is just to make sure retimed signal is being routed to the 100-ohm output. Do we still observe bit error? 

    Also, through TI internal email please send me your customer schematic.

    Regards,, Nasser 

  • 0 in reply to Nasser Mohammadi
    TI__Expert 4750 points

    Hi Nasser,

    With a normal pattern the LMH1297 has been working properly all the weekend (52 hours) without errors or signal loss.

    With exactly the same configuration and a pathological pattern there are about many signal losses and errors per minute.

     

    Regards,

  • 0 in reply to TISL
    TI__Guru* 93570 points

    Hi TISL,

    1). Through internal TI email, please send me your customer schematic.

    2). On OUT0 please make sure de-emphasis is disabled. Sometimes this may cause over-equalization on the receiver.

    3). Please make sure on the receiver we have minimum or no equalization.

    4). Under this condition, when we are receiving error due to the pathological pattern, please send me LMH1297 register contents.

    Regards,, Nasser

  • 0 in reply to Nasser Mohammadi
    TI__Expert 4750 points

    Hi Nasser,

    1) the tests are done with our EVM

    2) the results are the same:

    3) the customer told ma that he can't disable equalization. For information, the previous screenshot (June 8th) were taken with 60m of cable in both cases.

    4) see attached

    Regards,lmh1297_config.cfg

  • 0 in reply to TISL
    TI__Guru* 93570 points

    Hi TISL,

    Please attached note a new configuration register setting(you may need to change the file extension to .cfg), please use this register setting, and let me know the result.

    Please make sure we power down SDI_OUT.

    At the end, please send me the register settings when you are getting bit errors. Also please specify cable length you used for your test.

    Regards,,, Nasser

    Fullscreen lmh1297_config_2.txt Download 
    0x0	Shared Registers_Reserved0	00
0x1	Shared Registers_Reserved1	0B
0x2	Shared Registers_Reserved2	02
0x3	Shared Registers_Reserved3	00
0x4	Shared Registers_Reset Share Regs	01
0x5	Shared Registers_Reserved4	00
0x6	Shared Registers_Reserved5	00
0x7	Shared Registers_Reserved6	04
0x8	Shared Registers_Reserved7	11
0x9	Shared Registers_Reserved8	01
0xE2	Shared Registers_Reset Share/Channel Regs	10
0xF0	Shared Registers_Device Revision	00
0xF1	Shared Registers_Device_ID	6B
0xFE	Shared Registers_I/O Direction and Output Power-Down Control	2A
0xFF	Shared Registers_Register Communication Control	05
0x0	CTLE-CDR Registers_Reset CTLE/CDR Registers	00
0x1	CTLE-CDR Registers_LOS Status	02
0x2	CTLE-CDR Registers_CDR_Status	80
0x3	CTLE-CDR Registers_IN0 Manual EQ Boost	80
0x4	CTLE-CDR Registers_Reserved0	00
0x5	CTLE-CDR Registers_Reserved1	00
0x6	CTLE-CDR Registers_Reserved2	00
0x7	CTLE-CDR Registers_Reserved3	00
0x8	CTLE-CDR Registers_Reserved4	00
0x9	CTLE-CDR Registers_Output Mux Override Control	20
0xA	CTLE-CDR Registers_CDR Reset Control	50
0xB	CTLE-CDR Registers_Reserved5	1F
0xC	CTLE-CDR Registers_CDR Output Status Control	08
0xD	CTLE-CDR Registers_Reserved6	00
0xE	CTLE-CDR Registers_Reserved7	B3
0xF	CTLE-CDR Registers_Reserved8	69
0x10	CTLE-CDR Registers_Reserved9	27
0x11	CTLE-CDR Registers_EOM Voltage Range Control	E0
0x12	CTLE-CDR Registers_Reserved10	A0
0x13	CTLE-CDR Registers_IN0 CTLE Control	80
0x14	CTLE-CDR Registers_Reserved11	00
0x15	CTLE-CDR Registers_IN0 Signal Detect Power Down and Threshold Setting	00
0x16	CTLE-CDR Registers_Reserved12	25
0x17	CTLE-CDR Registers_Reserved13	25
0x18	CTLE-CDR Registers_Reserved14	40
0x19	CTLE-CDR Registers_Reserved15	00
0x1A	CTLE-CDR Registers_Reserved16	A0
0x1B	CTLE-CDR Registers_Reserved17	03
0x1C	CTLE-CDR Registers_OUT0 Mux Select_0	58
0x1D	CTLE-CDR Registers_Reserved18	00
0x1E	CTLE-CDR Registers_OUT Mux Select_1	E9
0x1F	CTLE-CDR Registers_OUT0 Inversion	10
0x20	CTLE-CDR Registers_Reserved19	00
0x21	CTLE-CDR Registers_Reserved20	00
0x22	CTLE-CDR Registers_Reserved21	00
0x23	CTLE-CDR Registers_HEO_VEO_OV	40
0x24	CTLE-CDR Registers_EOM Control	02
0x25	CTLE-CDR Registers_EOM_MSB	00
0x26	CTLE-CDR Registers_EOM_LSB	00
0x27	CTLE-CDR Registers_HEO	1C
0x28	CTLE-CDR Registers_VEO	40
0x29	CTLE-CDR Registers_Auto EOM Voltage Range	20
0x2A	CTLE-CDR Registers_EOM_timer_thr	30
0x2B	CTLE-CDR Registers_Reserved22	00
0x2C	CTLE-CDR Registers_VEO Scale	72
0x2D	CTLE-CDR Registers_CTLE Boost Override	00
0x2E	CTLE-CDR Registers_Reserved23	00
0x2F	CTLE-CDR Registers_Reserved24	06
0x30	CTLE-CDR Registers_Reserved25	00
0x31	CTLE-CDR Registers_IN0 Adaptation Mode and Input Mux Select	20
0x32	CTLE-CDR Registers_HEO/VEO Interrupt Threshold	11
0x33	CTLE-CDR Registers_Reserved26	88
0x34	CTLE-CDR Registers_Reserved27	BF
0x35	CTLE-CDR Registers_Reserved28	1F
0x36	CTLE-CDR Registers_Reserved29	11
0x37	CTLE-CDR Registers_Reserved30	00
0x38	CTLE-CDR Registers_Reserved31	00
0x39	CTLE-CDR Registers_Reserved32	00
0x3A	CTLE-CDR Registers_Low Data Rate IN0 EQ Boost	00
0x3B	CTLE-CDR Registers_Reserved33	44
0x3C	CTLE-CDR Registers_Reserved34	F6
0x3D	CTLE-CDR Registers_Reserved35	00
0x3E	CTLE-CDR Registers_HEO_VEO Lock Monitor Enable	80
0x3F	CTLE-CDR Registers_Pin Override Register Control	09
0x40	CTLE-CDR Registers_IN0 Index 0 Boost for Adaptation	00
0x41	CTLE-CDR Registers_IN0 Index 1 Boost for Adaptation	40
0x42	CTLE-CDR Registers_IN0 Index 2 Boost for Adaptation	80
0x43	CTLE-CDR Registers_IN0 Index 3 Boost for Adaptation	50
0x44	CTLE-CDR Registers_IN0 Index 4 Boost for Adaptation	C0
0x45	CTLE-CDR Registers_IN0 Index 5 Boost for Adaptation	90
0x46	CTLE-CDR Registers_IN0 Index 6 Boost for Adaptation	54
0x47	CTLE-CDR Registers_IN0 Index 7 Boost for Adaptation	A0
0x48	CTLE-CDR Registers_IN0 Index 8 Boost for Adaptation	B0
0x49	CTLE-CDR Registers_IN0 Index 9 Boost for Adaptation	95
0x4A	CTLE-CDR Registers_IN0 Index 10 Boost for Adaptation	69
0x4B	CTLE-CDR Registers_IN0 Index 11 Boost for Adaptation	D5
0x4C	CTLE-CDR Registers_IN0 Index 12 Boost for Adaptation	99
0x4D	CTLE-CDR Registers_IN0 Index 13 Boost for Adaptation	A5
0x4E	CTLE-CDR Registers_IN0 Index 14 Boost for Adaptation	E6
0x4F	CTLE-CDR Registers_IN0 Index 15 Boost for Adaptation	F9
0x50	CTLE-CDR Registers_Reserved36	00
0x51	CTLE-CDR Registers_Reserved37	00
0x52	CTLE-CDR Registers_IN0 Active EQ Readback	00
0x53	CTLE-CDR Registers_Reserved38	00
0x54	CTLE-CDR Registers_Interrupt Status Register	80
0x55	CTLE-CDR Registers_Reserved39	02
0x56	CTLE-CDR Registers_Interrupt Control Register	00
0x60	CTLE-CDR Registers_Reserved40	26
0x61	CTLE-CDR Registers_Reserved41	31
0x62	CTLE-CDR Registers_Reserved42	70
0x63	CTLE-CDR Registers_Reserved43	3D
0x64	CTLE-CDR Registers_Reserved44	FF
0x65	CTLE-CDR Registers_Reserved45	00
0x66	CTLE-CDR Registers_Reserved46	00
0x67	CTLE-CDR Registers_Reserved47	00
0x68	CTLE-CDR Registers_Reserved48	00
0x69	CTLE-CDR Registers_HEO_VEO Lock Monitor	0A
0x6A	CTLE-CDR Registers_VEO and HEO Lock Threshold	44
0x6B	CTLE-CDR Registers_Reserved49	40
0x6C	CTLE-CDR Registers_Reserved50	00
0x6D	CTLE-CDR Registers_Reserved51	00
0x6E	CTLE-CDR Registers_Reserved52	00
0x6F	CTLE-CDR Registers_Reserved53	00
0x70	CTLE-CDR Registers_Reserved54	03
0x71	CTLE-CDR Registers_Reserved55	20
0x72	CTLE-CDR Registers_Reserved56	00
0x73	CTLE-CDR Registers_Reserved57	00
0x74	CTLE-CDR Registers_Reserved58	00
0x75	CTLE-CDR Registers_Reserved59	00
0x77	CTLE-CDR Registers_Reserved60	00
0x80	CTLE-CDR Registers_Reserved61	00
0x81	CTLE-CDR Registers_Reserved62	00
0x82	CTLE-CDR Registers_Reserved63	00
0x83	CTLE-CDR Registers_Reserved64	00
0x84	CTLE-CDR Registers_Reserved65	00
0x85	CTLE-CDR Registers_Reserved66	00
0x87	CTLE-CDR Registers_Reserved67	00
0x90	CTLE-CDR Registers_Reserved68	A5
0x91	CTLE-CDR Registers_Reserved69	23
0x92	CTLE-CDR Registers_Reserved70	2C
0x93	CTLE-CDR Registers_Reserved71	32
0x94	CTLE-CDR Registers_Reserved72	37
0x95	CTLE-CDR Registers_Reserved73	3E
0x98	CTLE-CDR Registers_Reserved74	3F
0x99	CTLE-CDR Registers_Reserved75	04
0x9A	CTLE-CDR Registers_Reserved76	04
0x9B	CTLE-CDR Registers_Reserved77	01
0x9C	CTLE-CDR Registers_Reserved78	01
0x9D	CTLE-CDR Registers_Reserved79	04
0x9E	CTLE-CDR Registers_Reserved80	04
0xA0	CTLE-CDR Registers_SMPTE Data Rate Lock Enable	1F
0x0	Config IO Registers_Reset ConfigIO Registers	08
0x1	Config IO Registers_EQ Observation Status	45
0x2	Config IO Registers_Rate and Driver Observation Status	E3
0x3	Config IO Registers_MUTERef Control	3F
0x4	Config IO Registers_Reserved0	00
0x5	Config IO Registers_Reserved1	00
0x6	Config IO Registers_Reserved2	B4
0x7	Config IO Registers_Reserved3	3F
0x8	Config IO Registers_Reserved4	27
0x9	Config IO Registers_Reserved5	01
0xA	Config IO Registers_Reserved6	05
0xB	Config IO Registers_Reserved7	37
0xC	Config IO Registers_Reserved8	01
0xD	Config IO Registers_Reserved9	25
0xE	Config IO Registers_Reserved10	37
0xF	Config IO Registers_Reserved11	02
0x10	Config IO Registers_Reserved12	1E
0x11	Config IO Registers_Reserved13	02
0x12	Config IO Registers_Reserved14	04
0x13	Config IO Registers_Reserved15	04
0x14	Config IO Registers_Reserved16	3C
0x15	Config IO Registers_Reserved17	00
0x16	Config IO Registers_Reserved18	00
0x17	Config IO Registers_Reserved19	04
0x18	Config IO Registers_Reserved20	41
0x19	Config IO Registers_Reserved21	04
0x1A	Config IO Registers_Reserved22	01
0x1B	Config IO Registers_Reserved23	A7
0x1C	Config IO Registers_Reserved24	03
0x1D	Config IO Registers_Reserved25	00
0x1E	Config IO Registers_Reserved26	54
0x1F	Config IO Registers_Reserved27	00
0x20	Config IO Registers_Reserved28	00
0x21	Config IO Registers_Reserved29	C2
0x22	Config IO Registers_Reserved30	00
0x23	Config IO Registers_Reserved31	00
0x24	Config IO Registers_Reserved32	00
0x25	Config IO Registers_Cable Length Indicator	0C
0x26	Config IO Registers_Reserved33	02
0x27	Config IO Registers_EQ Bypass and MuteRef Override	08
0x28	Config IO Registers_Reserved34	00
0x29	Config IO Registers_Reserved35	3F
0x2A	Config IO Registers_Reserved36	40
0x2B	Config IO Registers_Reserved37	89
0x2C	Config IO Registers_Reserved38	0B
0x2D	Config IO Registers_Reserved39	00
0x2E	Config IO Registers_Reserved40	00
0x2F	Config IO Registers_Reserved41	04
0x30	Config IO Registers_OUT0 Output Control	0A
0x31	Config IO Registers_OUT0 De-Emphasis Control	31
0x32	Config IO Registers_Reserved42	00
0x33	Config IO Registers_Reserved43	00
0x34	Config IO Registers_Splitter_Reg	17
0x35	Config IO Registers_Reserved44	83
0x36	Config IO Registers_Reserved45	02
0x37	Config IO Registers_Reserved46	00
0x38	Config IO Registers_Reserved47	00
0x39	Config IO Registers_Reserved48	00
0x3A	Config IO Registers_Reserved49	00
0x3B	Config IO Registers_Reserved50	00
0x3C	Config IO Registers_Reserved51	00
0x3D	Config IO Registers_Reserved52	7F
0x3E	Config IO Registers_Reserved53	00
0x3F	Config IO Registers_Reserved54	00
0x40	Config IO Registers_Reserved55	00
0x41	Config IO Registers_Reserved56	0F
0x42	Config IO Registers_Reserved57	00
0x43	Config IO Registers_Reserved58	01
0x44	Config IO Registers_Reserved59	00
0x45	Config IO Registers_Reserved60	00
0x46	Config IO Registers_Reserved61	00
0x47	Config IO Registers_Reserved62	00
0x48	Config IO Registers_Reserved63	00
0x49	Config IO Registers_Reserved64	08
0x4A	Config IO Registers_Reserved65	10
0x4B	Config IO Registers_Reserved66	10
0x4C	Config IO Registers_Reserved67	00
0x4D	Config IO Registers_Reserved68	00
0x4E	Config IO Registers_Reserved69	00
0x4F	Config IO Registers_Reserved70	00
0x50	Config IO Registers_Reserved71	00
0x51	Config IO Registers_Reserved72	00
0x52	Config IO Registers_Reserved73	00
0x53	Config IO Registers_Reserved74	00
0x54	Config IO Registers_Reserved75	2F
0x60	Config IO Registers_SDI_IO Driver Power Down and Slew Rate Control	C1
0x61	Config IO Registers_SDI_IO Output Control	58
0x62	Config IO Registers_SDI_IO Pre-emphasis and Polarity Control	50
0x67	Config IO Registers_SDI_OUT Slew Rate Control	01
0x68	Config IO Registers_SDI_OUT Output Control	58
0x69	Config IO Registers_SDI_OUT Pre-emphasis and Polarity Control	10
     

  • 0 in reply to Nasser Mohammadi
    TI__Expert 4750 points

    Hi Nasser,

    The results are the same. The cable length is 60 m.

    This behavior only happens with pathological patterns.

     

    As the EVM is at least 2 or 3 years old, is there any possibility that the IC that is mounted in the EVM is a preliminary version of the LMH1297?
     

    The customer think that the problem is related with the high frequency (100kHz) jitter of the output signal. With pathological patterns this jitter is over 0.3 UI and maybe the receivers are not able to recover the signal without errors or signal losses.

    Any thoughts on this?

    Is it something we can reproduce on our side?

    Attached is the register settings.

    Regards,

    lmh1297_config_3.cfg

  • 0 in reply to TISL
    TI__Guru* 93570 points

    Hi TISL,

    I believe customer is right. The issue is related to the pathological low frequency energy content. Pathological pattern has a much wider bandwidth versus color bar for example. Additionally there is DC wander - unlike color bar - and device has to track this DC wander.

    If you like, you can send me your customer LMH1297 evaluation board and i can check in the lab.

    Also, I checked the attached register setting above. It seems signal or cable is not attached to the device. I say this since ConfigIO register 0x25 - cable length indicator - shows 0x00. Also, ConfigIO register 0x02 shows loss of signal.

    Regards,, nasser

  • 0 in reply to Nasser Mohammadi
    TI__Expert 4750 points

    Hi Nasser,

    The tests are just done with our EVM. Do you need them to send it to you.

    FYI, it has also been performed with a competitor EVM, which works well.

    Bellow, the customer made two more measurements with the 1297 EVM, 60 m of cable and pathological signals.

     

    The difference between the two measurements is the polarity of the pathological pattern, in one case the pathological pattern is composed of nineteen 0s and one 1 and in the other case of nineteen 1s and one 0.

     

    The oscilloscope screenshots are taken triggering with the Phabrix GPO that indicates the pathological pattern on the 12G signal.

    The yellow trace is the GPO and the green trace is the data signal. You can see appreciate the pathological pattern with different polarities in the two figures.

     

    When the nineteen 0s and one 1 pathological pattern is generated, the LMH1297 the jitter is 0.35 UI and the Phabrix does not report signal losses as you can see in one of the Phabrix's screenshots.

    In the case of the nineteen 1s and one 0 the jitter is 0.42 UI and the Phabrix is continuously losing the signal as you can also see in the other Phabrix's screenshots.

    In both cases the jitter figure is over the 0.3 UI that the SMPTE ST 2082-1 requires.

    Regards,

  • 0 in reply to TISL
    TI__Guru* 93570 points

    Hi TISL,

    Please note SMPTE clearly specifies that we have to use color bar for jitter measurement. Please note SMPTE 2082-1 12G SDI wordings: "Color bars are chosen as a non-stressing test signal for jitter measurements. Use of a stressing signal with long runs of zeros could give misleading results."

    Can you please send me email at nasser.mohammadi@ti.com so we work on closing this issue.

    Regards,, nasser