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TSB43AB23: Interrupt Event Register bit18 (regAccessFail)

K.Yaita
Guru 29720 points
Part Number: TSB43AB23


Hi Team,

I would like to ask about Interrupt Event Register bit18 (regAccessFail).



Could you tell me how to handle (debug) when regAccessFail is set "1"?
I would also like to know if "SCLK clock signal from the PHY layer" is internal signal of TSB43AB23 or not.

The background of the question is my customer is facing the situation when accessing specific OHCI address.

Best Regards,
Yaita

  • 0
    TI__Guru**** 179171 points

    Yaita-san

    SCLK is an internal clock signal from the PHY to the LLC. Are you setting the LPS to a "1"?

    When the TSB43AB23 device is in the low-power mode, the internal 49.153-MHz clock becomes active (and the integrated PHY layer becomes operative) within 2 ms after bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1.

    Thanks

    David