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SN65DSI86: SN65DSI86: Keep the ASSR settings with the TEST2 pin pulled high

Arturo Esteban Vazquez Gutierrez
Prodigy 200 points
Part Number: SN65DSI86
Other Parts Discussed in Thread: TEST2

Hello

We are using the SN65DSI86 bridge and the set up that we are working with is the next:

Processor -> DSI to DP bridge -> USB-C connector -> USB-C to HDMI adapter -> HDMI monitor

Our first circuit revision had the TEST2 pin tied directly to ground so we worked with an USB-C to HDMI adapter that was ASSR compatible to get video transmission, now our newest board revision has the TEST2 pin pulled high to make the ASSR feature selectable, until this point the driver source code has not been modified.

After performing some tests with our new board we noticed that the previously described setup reports a link training failure, we thought that with the pull up on the TEST2 pin the original behavior wouldn’t change and only if it was necessary the ASSR settings could be overridden.

With the TEST2 pin pulled high is there any additional settings needed to keep the ASSR compatibility?

 

Thanks,

Esteban V.

  • 0
    TI__Guru**** 178816 points

    Esteban V.

    ======ASSR RW control ====== 

    <i2c_write addr=0x2D count=1 radix=16> FF 7 </i2c_write>/>
    <i2c_write addr=0x2D count=1 radix=16> 16 1 </i2c_write>/>
    <i2c_write addr=0x2D count=1 radix=16> FF 0 </i2c_write>/>

    ===== Enhanced Frame, Vstream Enable, Standard DP scrambler seed ======
    <i2c_write addr=0x2D count=1 radix=16> 5A 0C </i2c_write>/>

    ===== Enhanced Frame, Vstream Enable, ASSR scrambler seed ====== 
    <i2c_write addr=0x2D count=1 radix=16> 5A 0D </i2c_write>/>

    What link training error are you seeing?

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 200 points

    Hi, David

    Thank you for the quick response, We have performed the i2c procedure that you attached and we can override the 0x5A register ASSR_CONTROL bits successfully, but until now, even if we left the ASSR settings untouched and using an ASSR compatible device we see a: “redriver semi auto link training failure”, the link remains off. We are using this kind of training because our board has a redriver between the SN65DSI86 bridge and the DisplayPort output. This set up used to work on our previous board revision. Are there any other settings that we must consider when having the pull up on the TEST2 pin?

    Best regards,

    Esteban V.

  • 0 in reply to Arturo Esteban Vazquez Gutierrez
    TI__Guru**** 178816 points

    Esteban

    Could you please dump out register 0xF0 to 0XF8 when redriver semi auto link training reported a failure? 

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Prodigy 200 points

    Hi, David

    This is our i2c register map, any information that you could provide us will be helpful.

            0  1   2   3   4   5   6   7   8   9    a  b   c    d   e   f 

    00: 36 38 49 53 44 20 20 20 02 00 03 00 00 00 00 00

    10: 26 00 4c 4c 00 00 00 00 00 00 00 00 00 00 00 00..

    20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

    30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

    40: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 

    50: 00 00 00 00 00 00 20 00 40 e4 05 00 10 00 30 00 

    60: a0 60 a4 00 01 00 00 00 00 00 00 00 00 00 00 00 

    70: 00 00 00 00 00 06 00 00 80 00 00 00 00 00 00 00

    80: 00 00 00 00 00 00 00 00 00 1f 7c f0 c1 07 1f 7c

    90: f0 c1 07 24 e0 00 00 04 01 00 00 00 00 00 00 00 

    a0: 01 ff ff 00 00 00 00 00 00 00 00 00 00 00 00 00 

    b0: 04 78 ac ac 08 6c 9c 9c 0c 5c 5c 5c 0c 0c 0c 0c 

    c0: 3f 3f 0f 00 00 00 00 00 00 00 00 00 00 00 00 00

    d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

    e0: 01 00 00 00 00 00 06 00 00 00 00 00 00 00 00 00 .

    f0: 02 2b 00 00 09 00 00 00 02 00 00 00 00 00 00 00 

    Thanks,

    Esteban V.

  • 0 in reply to Arturo Esteban Vazquez Gutierrez
    TI__Guru**** 178816 points

    Esteban V.

    Do you see link training successful with these two I2C command sequences?

    Command sequence 1

    ======ASSR RW control ====== 

    <i2c_write addr=0x2D count=1 radix=16> FF 7 </i2c_write>/>
    <i2c_write addr=0x2D count=1 radix=16> 16 0 </i2c_write>/>
    <i2c_write addr=0x2D count=1 radix=16> FF 0 </i2c_write>/>

    Command sequence 2

    ======ASSR RW control ====== 

    <i2c_write addr=0x2D count=1 radix=16> FF 7 </i2c_write>/>
    <i2c_write addr=0x2D count=1 radix=16> 16 1 </i2c_write>/>
    <i2c_write addr=0x2D count=1 radix=16> FF 0 </i2c_write>/>

    ===== Enhanced Frame, Vstream Enable, ASSR scrambler seed ====== 

    <i2c_write addr=0x2D count=1 radix=16> 5A 0D </i2c_write>/>

    These two command sequences should behave the same as your first board build (TEST2 pin pulled low). 

    The register dump shows various errors on DSI Channel A plus link training error. For the DSI channel A errors, can you please clear the error by writing 0xFF to registers 0xF0 and 0xF1, and then read the registers again? I want to make sure these are real errors. 

    For the link training error, does the DSI86 color bar mode work in your design?

    Which redriver do you use between the DSI86 and the DP output?

    Thanks

    David