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DS90UB941AS-Q1: V sync problem

Yuri Oreshnikov
Intellectual 260 points
Part Number: DS90UB941AS-Q1


Hello. There is pair DS9UB941 and DS90UB926. Test patterns with internal and with internal/w.Ext clock works well from each other IC. But when we set "External" as a timing clock in DS90UB941 test pattern mode does not work. There is not VSync clock at DS90UB926 but pclk, de, hs signals exist. So there is not VSync clock at real picture. Sometimes I see strange pulses at VSync pin. DSI source is DSI_VIDEO_CLOCK_CONTINUOUS, DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END. What and where I need to change to get VSync signal?



  • 0
    TI__Mastermind 19720 points

    Hi Yuri,

    Is the 941AS linked to 2 926's or just 1? I have encountered issues before where the DSI source has not been outputting Vsync's can you check and make sure that your DSI source is outputting Vsync?

    Regards,

    Michael W.

  • 0 in reply to Michael.Walker
    Intellectual 260 points

    Hi Michael

    Now we connect just 1 926, when it will work we connect second. Unfortunately I can not watch DSI signals, and I dont know is there Hsync or not. I use next config of dsi

    dsi-pkt-seq =
    <CMD_VS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>,
    <CMD_VE LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>,
    <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>,
    <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT CMD_BLNK LEN_HBP CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>,
    <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>,

    <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT CMD_BLNK LEN_HBP CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>;

    But I can not find any information is it right or not and what the right packet sequence I have to write for DS90UB941.

  • 0 in reply to Yuri Oreshnikov
    TI__Mastermind 19720 points

    Hi Yuri,

    What do you mean when you say " Sometimes I see strange pulses at VSync pin"? What do you mean by strange? when are the pulses? you dont see any other VSync pulses out of the 926 when regular video is sent.

    Can you read the values for the following registers? DSI_CONFIG_0, DSI_HSYNC_WIDTH_HI, DSI_HSYNC_WIDTH_LO, DSI_VSYNC_WIDTH_HI, DSI_VSYNC_WIDTH_LO ? 

    What is the DSI source?

    Regards,

    Michael W.

  • 0 in reply to Michael.Walker
    Intellectual 260 points

    Hi Michael,

    I dont know what I did but when I wrote next dsi source config (in linux device tree file):

    dsi-pkt-seq =

    <CMD_VS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>,
    <CMD_VE LEN_SHORT CMD_BLNK LEN_HSYNC CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>,
    <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>,
    <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT CMD_BLNK LEN_HBP CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>,
    <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT PKT_LP LINE_STOP>,

    <CMD_HS LEN_SHORT CMD_BLNK LEN_HSYNC CMD_HE LEN_SHORT CMD_BLNK LEN_HBP CMD_RGB_24BPP LEN_HACTIVE3 CMD_BLNK LEN_HFP LINE_STOP>;

    , Vsync appeared. And now everything work fine with 1 926 and with 2 926's in left right split mode.

    Thanks.