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SN65DSI86: Errors and modelines

Part Number: SN65DSI86

Dear team,

We have a board with a i.MX8M Mini SoC connected to the SN65DSI86.

The SN65DSI86 is clocked with an external oscillator (26MHz), and the connection to the SoC is via 4 MIPI DSI lanes on channel A.

The SoC is running Linux 4.19.35, we have backported the Linux upstream driver to linux-imx 4.19.35, and we have made some tweaks to it to make it suitable to work with a DisplayPort connector (HPD support, EDID readback via native AUX commands, probing of panel capabilities via DCPD through AUX native commands, etc.).

We are observing two main issues:

* some error bits are set in registers 0xf0 and 0xf1

* we have some problems with some of the modelines returned by the monitor

Errors

=====

Errors  CHA_SOT_SYNC_ERR, CHA_SOT_BIT_ERR and CHA_DSI_PROTOCOL_ERR are always set, we tried clearing up the errors after the video stream starts flowing but they get set back straight away.

At times we get error CHA_INVALID_LENGTH_ERR as well, but this error doesn't come back when cleared.

Do you guys have any idea what could cause those errors to appear? Problems with the PCB or problems with the way the SoC is generating the DSI signals?

Modelines

========

We are able to get a valid EDID from the monitor, and we have validated the EDID content with another Linux system known to work connected to the same monitor.

Some of the modelines don't work at all for us (the monitor rejects the video input), others seem to work fine, others have some weird tearing in them.

For example, modeline:

"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5

is the preferred resolution reported by the monitor we use for testing, with such a modeilne the monitor refuses to display anything, but if we use modeline:

"1920x1080" 60 172780 1920 2040 2248 2576 1080 1081 1084 1118 0x20 0x6

the monitor is happy.

Any idea as to what could cause this?

Also, the EDID is reporting a maximum dotclock of 170MHz, but modeline:

"1920x1080" 60 172780 1920 2040 2248 2576 1080 1081 1084 1118 0x20 0x6 

is using a dotclock higher than the one reported by the monitor.

Any help is very much appreciated.

Thanks,

Fabrizio

  • Fabrizio

    If you are seeing consistent errors in register 0xF0 and 0xF1, then there could be signal integrity issue with the DSI lanes. You can change the RX equalizer setting at register 0x11 to see if improves the signal integrity. If the RX equalizer does not clear the errors being reported, then we need to probe DSI lanes to see if there is a setup and hold violation, or general signal integrity problem.

    When you are reading back the EDID info, are you re-programming the DSI86 Video Registers? The DSI86 expects the parameters in Table 7 of its datasheet to be programmed. The DSI86 will then use these parameters to determine the DisplayPort MSA parameters that are transmitted over DisplayPort every vertical blanking period. These MSA parameters are used by the monitor to recreate the video format provided on the DSI interface.

    Thanks

    David

  • Hi David,

    sorry for the late reply. We discovered that the problem was down to the way the DSI signals were being generated from the SoC side of things.

    Thank you for your help!

    Fabrizoi