TLK10034: Connecting the HS side to an optical transceiver

Michael Nycz

Part Number: TLK10034
Other Parts Discussed in Thread: TLK10232

We have a new design where we are using the TLK10034. We have four lanes of XAUI and on the high speed side we have the four lanes tied to optical transceivers. This design is very similar to one that we had done using the TLK10232 chip. On the TLK10232 design, we found that we needed to turn off autonegotiation and link training in order for the HS side to work properly since there would be no AN on the optical path.To do that we set the following registers....

DEV Address 0x07, Register Address 0x0000 Default value = 0x3000 and we set it to 0x2000 (changing bit 12 from 1 to 0.

Also,

DEV Address 0x01 Register Address 0x0096 Default value = 0x0002 and we set it to 0x0000 (changing bit 1 from 1 to 0.

We then followed the above with a reset....

DEV Address 0x1E Register Address 0x000E Default value= 0x000 and we set it to 0x000E Where bits 3:1 initiate the reset.

When we do this on the TLK10232, this does what we need and we are able to send data from the XAUI port through the TLK10232, through the optical transceiver and all is good.

When we go to the TLK10034, this does not seem to work. We've tried both low side and high side loop back modes and in both cases these work. So we are confident that all of the connections from the TLK10034 are correct and complete. However, when we try to loop the XAUI between two channels (1 and 2) and then ping from two servers on the optical side, there is no transferring of data.

My question is...

In looking through both datasheets, it appears that the same register changes described above would produce a similar function on both chips. The big difference between the two chips appears to be that one is a 2 channel device and the other is a four channel device. In practice, making the above changes works for the TLK10232. It is not working for the TLK10034. Are there any other settings that would need to be changed to allow the TLK10034 to work as a XAUI to optical signal system?

Any help with this would be greatly appreciated.

over 5 years ago

0 Rodrigo Natal over 5 years ago

TI__Mastermind 19235 points

Hi,

I'd suggest doing configuration sanity check per below.

Make sure the REF_CLK and serdes multiplier settings are set correctly for 10G KR rate

Table 5-1. Specific Line Rate and Reference Clock Selection for the 10GBASE-KR Mode

LOW SPEED SIDE				HIGH SPEED SIDE
Line Rate (Mbps)	SERDES PLL Multiplier	Rate	REFCLKP/N (MHz)	Line Rate (Mbps)	SERDES PLL Multiplier	Rate	REFCLKP/N (MHz)
3125	10	Full	156.25	10312.5	16.5	Full	156.25
3125	5	Full	312.5	10312.5	8.25	Full	312.5

Double check your mode select and ST settings to ensure configuration for 10G operation without auto-neg

The TLK10034 is a versatile high-speed transceiver device that is designed to perform various physical

layer functions in three operating modes: 10GBASE-KR Mode, 1G-KX Mode, and General Purpose (10G) SERDES Mode. The three modes are described in three separate sections. The device operating mode is determined by the MODE_SEL and ST pin settings, as well as bit MDIO bit 30.1.10.

Table 5-13. TLK10034 Operating Mode Selection

	ST = 0 (Clause 45)	ST = 1 (Clause 22)
{MODE_SEL pin, SW bit (30.1.10)}
1x	10G	10G
01	10G	10G
00	10G-KR/1G-KX (Determined by Auto Neg)	1G-KX (No Auto Neg)

As per the TLK10034 datasheet: Each channel of the TLK10034 can be used to convert between XAUI (on the low speed port) and 10GBASE-R signaling (on the high speed port). The high speed side of the device meets the requirements of the 10GBASE-KR physical layer standard for 10 Gbps data transmission over a PCB backplane. The device can also be used for optical physical layers (like 10GBASE-SR or 10GBASE-LR) by interfacing to optical modules requiring SFI or XFI electrical signaling. For optical use cases, KR-specific features like Clause 73 auto-negotiation and link training should be disabled.
- Link training may be disabled via 0x0096 bit 1

Table 5-86. KR_TRAIN_CONTROL

Device Address: 0x01 Register Address: 0x0096 Default: 0x0002
Bit	Name	Description	Access
1	KR_TRAINING_ENABLE	1 = Enable 10GBASE-KR start-up protocol (Default 1’b1) 0 = Disable 10GBASE-KR start-up protocol	RW
0	KR_RESTART_TRAINING	1 = Reset 10GBASE-KR start-up protocol 0 = Normal operation (Default 1’b0)	RW/SC

See below auto-neg control registers. Auto-neg may be disabled via register 0x0000 bit 12

Device Address: 0x07 Register Address: 0x0000 Default: 0x3000
Bit	Name	Description
15	AN_RESET	1 = Resets Auto Negotiation 0 = Normal operation (Default 1’b0)
13	RESERVED	For TI use only (Default 1’b1)
12	AN_ENABLE	1 = Enable Auto Negotiation (Default 1’b1) 0 = Disable Auto Negotiation
9	AN_RESTART	1 = Restart Auto Negotiation 0 = Normal operation (Default 1’b0) If set, a read of this register is required to clear AN_RESTART bit.

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TLK10034: Connecting the HS side to an optical transceiver