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DP83826I: Inquiries about Power Supply Sequence etc.

Jin Ikeda
Expert 6420 points
Part Number: DP83826I

Hello Team,

I have inquiries about DP83826I.

(1) DP83826 & DP83822 have similar specifications. What is the background of  DP83826I development ?

(2) About the power supply sequence.
In customer's application, the clock is not input to XI during 3.3V power rising.


I belive the following sequence is required to keep the instruction "Clock shall be available at power ramp, else additional RESET_N is needed".

1.  3.3V power supply (VDDIO, VDDA3V3) turns on. At this time, XI pin is fixed at 0C.
2. Clock input to XI.
3.  Reset release (Hardware RESET_N rise)

Is this sequence correct ?

(3) If fast link drop is enabled in the bootstrap of RX_D3, are the following three Fast Link down modes enabled?
• RX error count
• Low SNR threshold
• Descrambler link loss

(4 If RX_ER During IDLE = Disable (0x0A bit2 is 0), Will the link be down due to the RX error count condition even during the IDLE period?

When RX_ER During IDLE = Disable (0x0A bit2 is 0), I concern that  RX_ER will not be detected during IDLE, and then link down will not occur under the condition of RX error count.

Any advice will be appreciated.

Jin

  • 0
    TI__Expert 7040 points

    Hi Jin,

    Thank you for your questions,

    1) DP83826 and DP83822 are different design but both are targeted for industrial applications. Some of the differences are temperature grade, ESD, and Fiber Ethernet support. 

    2) The power sequence outline above is correct for powering the DP83826. 

    3) When Fast Link Drop is enabled RX error count and Low SNR threshold will be enabled and Descrambler link loss can be enable and configured through register 0x0131[5:0]

    I understand your question #4 and will still need a few days to confirm the RX_ER functionality with our validation team.

    Regards,

    Justin 

  • 0 in reply to Justin Lazaruk
    TI__Expert 7040 points

    Hi Jin,

    In reference to your question #4) above:

    When Fast Link Drop is enabled, the link should drop after the RX_ER error count is exceeded, even with RX_ER during idle disabled. 

    Regards,
    Justin 

  • 0 in reply to Justin Lazaruk
    TI__Expert 6420 points

    Hello Justin,

    Thanks for your help. I have additional inquiries to above 3) & 4)

     (3)

    If fast link drop is enabled in the bootstrap of RX_D3, are the following three Fast Link down modes enabled?

    • RX error count
    • Low SNR threshold
    • Descrambler link loss

    Your answer

    • 3) When Fast Link Drop is enabled RX error count and Low SNR threshold will be enabled and Descrambler link loss can be enable and configured through register 0x0131[5:0]

    After enabling Fast link drop in the bootstrap, when the CR3(0xB) register value was actually read, it was 0x040A. The register is not rewritten before reading. Since bit1, bit3 and bit10 are set to 1, from this result, it seems that Descrambler link loss is also enabled.
    As a reminder, if I enable fast link drop in the bootstrap, is there any doubt that Descrambler link loss is disabled by default? 
    About (4), I want to clarify below point.

    When 32 invalid symbols were received during the IDLE period, 32 RX error count was also counted up, and I wanted to know if link down due to fast link drop occurs.

    [Question]
    Suppose the following conditions are met.
    0x0B bit3 is 0 (The RX error count judgment is valid for the Fast Link Drop setting)
    0x0A bit 2 is 0 (RX_ER During IDLE = Disable)
    Under this condition, when 32 invalid data symbols are received during the IDLE period (RX_DV=Low period), RX error count also counts up and exceeds the threshold of the number of occurrences within 10us, Will PHY notify the linkdown to MAC side?
    Or, because 0x0A bit2 is 0, does RX error count itself not count up and PHY will NOT notify the linkdown to the MAC side?

    Any advice will be appreciated.

    Jin

  • 0 in reply to Jin Ikeda
    TI__Mastermind 26320 points

    1. When 32 invalid symbols were received during the IDLE period, 32 RX error count was also counted up, and I wanted to know if link down due to fast link drop occurs.

    Yes, the link drop will hapen. The flag is primarily to control the signal on RX_ER pin.

    2. Suppose the following conditions are met.
    0x0B bit3 is 0 (The RX error count judgment is valid for the Fast Link Drop setting)
    0x0A bit 2 is 0 (RX_ER During IDLE = Disable)
    Under this condition, when 32 invalid data symbols are received during the IDLE period (RX_DV=Low period), RX error count also counts up and exceeds the threshold of the number of occurrences within 10us, Will PHY notify the linkdown to MAC side?

    The link down will be raised thru register and interrupt ( if enabled)

    Or, because 0x0A bit2 is 0, does RX error count itself not count up and PHY will NOT notify the linkdown to the MAC side?

    Any link down detection shall get reflected on link-status and interrupt.

    Regards,
    Geet

  • 0 in reply to Geet Modi
    TI__Expert 6420 points

    Hello Geet,

    Thanks for your reply.

    Could you answer to below question ?

    If fast link drop is enabled in the bootstrap of RX_D3, are the following three Fast Link down modes enabled?

    • RX error count
    • Low SNR threshold
    • Descrambler link loss

             ----------------------------------------------------------------------------------------------------------------------------------

    answer on e2e

    • 3) When Fast Link Drop is enabled RX error count and Low SNR threshold will be enabled and Descrambler link loss can be enable and configured through register 0x0131[5:0]

      -----------------------------------------------------------------------------------------------------------------------------

    After enabling Fast link drop in the bootstrap, when the CR3(0xB) register value was actually read, it was 0x040A. The register is not rewritten before reading. Since bit1, bit3 and bit10 are set to 1, from this result, it seems that Descrambler link loss is also enabled.
    As a reminder, if I enable fast link drop in the bootstrap, is there any doubt that Descrambler link loss is disabled by default? 
    Any advice will be appreciated.
    Jin
  • 0 in reply to Jin Ikeda
    TI__Mastermind 26320 points

    on strapping FLD_En value in 0x000B = 0x040A which means all 3 counters are enabled:

    • RX error count
    • Low SNR threshold
    • Descrambler link loss

    Regards,

    Geet

  • 0 in reply to Geet Modi
    TI__Expert 6420 points

    Hello Geet,

    Thanks for your reply/

    I want to make sure.

    (1) If fast link drop is enabled in the bootstrap of RX_D3, are the following three Fast Link down modes enabled?

    • RX error count
    • Low SNR threshold
    • Descrambler link loss

    Previous answer on e2e was wrong and All those modes are enabled. Correct ?

    (2) When 32 invalid symbols were received during the IDLE period, 32 RX error count was also counted up, and I wanted to know if link down due to fast link drop occurs.

    Suppose the following conditions are met.
    0x0B bit3 is 0 (The RX error count judgment is valid for the Fast Link Drop setting)
    0x0A bit 2 is 0 (RX_ER During IDLE = Disable)
    Under this condition, when 32 invalid data symbols are received during the IDLE period (RX_DV=Low period), RX error count also counts up and exceeds the threshold of the number of occurrences within 10us, Will PHY notify the linkdown to MAC side?

    "The link down will be raised thru register and interrupt ( if enabled)"

    Does your answer mean that PHY doesn't notify the link down to Mac and  link down information is shown on register & Interrupt ? 

    I could not understand the meaning of "raised thru" on your comments. So please allow me to confirm.

    Best Regards,

    Jin

  • 0 in reply to Jin Ikeda
    TI__Mastermind 26320 points

    1. Yes, all modes are enabled.

    2. PHY will detect link down. It will indicate the link down thru all available interfaces : LED, Status Register, Interrupt.

    Regards,
    Geet