DP83867CR: Force Link Good bit was asserted. Why?

user6367771

Part Number: DP83867CR

Reg10.10, Force Link Good bit, was asserted after powering up.
But I didn't understand the reason.
Are there any possibilities?
The board strap (RX_CTRL) configuration disables AutoNegotiation.
This setting affects Force Link Good bit?

over 5 years ago

0 Vikram Sharma over 5 years ago

TI__Genius 16030 points

Hi,

Can you please share the following :

1. strap settings of rx_ctrl. What is the pull-up and pull-down resistor value.

2. Does this bit get cleared after writting :

a. reg<0x001F>=4000.

3. Are you writting any configuration to the phy after power up and then looking at this bit?

Regards,

Vikram

0 user6367771 over 5 years ago in reply to Vikram Sharma

Prodigy 40 points

Hi Vikram,

Thank you for reply.

1. Rh is 2.49K. Rl is open.

2. After power up, reg10 was 0x5448

I wrote 0x4000 in reg0x1f, and read reg10 again

But the value was 0x5448. No change

3. not 100% sure but I don't think so.

Linux was brought up but there is no device driver.

Any adviec?

Regards,

0 Vikram Sharma over 5 years ago in reply to user6367771

TI__Genius 16030 points

Hi,

Are you using 1Gbps mode? If yes then I see under strap table-5 that autoneg should always be enabled and hence your strap on rx_cntrl may not be valid.

I still need to hear back about the link between force-link-good bit and autoneg disable but do you see any functional issue when this bit is set?

Regards,

Vikram

0 user6367771 over 5 years ago in reply to Vikram Sharma

Prodigy 40 points

Hi Vikram,

I'm sorry for the shortage of our imformation.
I should have told you more precisely.
>do you see any functional issue when this bit is set?
Yes, I'm in trouble for link up.

Condition
STRAP pins RX_DV/RX_CTRL : MODE4(Autoneg Disable=1)
OS: Linux
Device driver: nothing

What I did was like following.

1) After powering up, connect ethernet cable and clear reset of DP83867
reg0x0 is 0x0140 (AutoNego is disabled)
reg0x10 is 0x5448 (Force Link Good is high)
Not linked up
2) Write 0x1140 to reg0x0 (Autoneg enable)
reg0x0 is 1140
reg0x10 is 0x5448
Not linked up
3) Write 0x5048 to reg0x10 (Force Link Good is Low)
Linked up!

Then, my question is three.
One is, do you think the procedure above is right way for link up?
Secondly, do you have any idea for the reason, the "Force Link Good" bit is high?
Thirdly, do you have any information why datasheet was revised and added the caution statement
"Autoneg Disable should always be set to 0 when using gigabit Ethernet" ?

Regards,
Koike

0 Vikram Sharma over 5 years ago in reply to user6367771

TI__Genius 16030 points

Hi Koike,

If mode of interest is 1Gbps, we recommend using forced mode for this (not auto-negotiation) for general purpose application.

Regards,

Vikram

0 user6367771 over 5 years ago in reply to Vikram Sharma

Prodigy 40 points

Hi Vikram,

I found the device driver for DP83867 and the source code says
/* After reset FORCE_LINK_GOOD bit is set. Although the
* default value should be unset. Disable FORCE_LINK_GOOD
* for the phy to work properly. */
So,it might have to be disabled after resetting PHY device.
But the datasheet doesn't say anything about this.

Rerads, Koike

0 Vikram Sharma over 5 years ago in reply to user6367771

TI__Genius 16030 points

Hi Koike,

Sorry for the confusion, I typed it wrong in my earlier reply and here is the correct statement :

If mode of interest is 1Gbps, we "don't" recommend using forced mode for this ("only" auto-negotiation) for general purpose application.

Regards,

Vikram

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DP83867CR: Force Link Good bit was asserted. Why?